MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 246
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Core Register Summary
6.11
6.11.1
6-28
Reset
52–63
32–46
49–51
SPR 1010
Bits
Bits
51
47
48
52
53
54
W
R
32
Name
CSLC (Data) Cache snoop lock clear. Sticky bit set by hardware if a dcbi snoop (either internally or externally
CPE
CLO
CUL
CPI
—
—
Name
L1 Cache Configuration Registers
ABE
—
L1 Cache Control and Status Register 0 (L1CSR0)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved, should be cleared.
(Data) Cache parity enable
0 Parity checking of the cache disabled
1 Parity checking of the cache enabled
(Data) Parity error injection enable
0 Parity error injection disabled
1 Parity error injection enabled. Cache parity must also be enabled (CPE = 1) when this bit is set.
Reserved, should be cleared.
generated) invalidated a locked cache line. Note that the lock bit for that line is cleared whenever the line is
invalidated. This bit can be cleared only by software.
0 The cache has not encountered a dcbi snoop that invalidated a locked line.
1 The cache has encountered a dcbi snoop that invalidated a locked line.
(Data) Cache unable to lock. Sticky bit set by hardware and cleared by writing 0 to this bit location.
0 Indicates a lock set instruction was effective in the cache
1 Indicates a lock set instruction was not effective in the cache
(Data) Cache lock overflow. Sticky bit set by hardware and cleared by writing 0 to this bit location.
0 Indicates a lock overflow condition was not encountered in the cache
1 Indicates a lock overflow condition was encountered in the cache
Address broadcast enable. The e500 broadcasts cache management instructions (dcbst, dcblc
(CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi) based on ABE. ABE must be set to
allow management of external L2 caches.
0 Address broadcasting disabled
1 Address broadcasting enabled
Reserved, should be cleared.
Figure 6-34. L1 Cache Control and Status Register 0 (L1CSR0)
—
Table 6-19. HID1 Field Descriptions (continued)
Table 6-20. L1CSR0 Field Descriptions
46
CPE CPI
47
48
All zeros
49
Description
—
Description
51
CSLC CUL CLO CLFR
52
Line Locking Bits
53
54
55
Access: Supervisor read/write
56
Freescale Semiconductor
—
61
CFI CE
62
63
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