MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 864
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Enhanced Three-Speed Ethernet Controllers
15.6.1.6
This section describes the reduced ten-bit interface (RTBI) intended to be used between the PHYs and the
eTSEC to implement a reduced-pin count version of a SerDes interface for optical-fiber devices in
1000BASE-SX/LX applications.
signals required to establish eTSEC module connection with a PHY. Note that in RTBI the eTSEC
immediately begins auto-negotiation with the SerDes.
A RTBI interface has 15 signals (GE_GTX_CLK125 included), as defined by the RGMII specification
Version 1.2a 9/22/00, and is intended to be an alternative to the IEEE 802.3u MII, the IEEE 802.3z GMII
and the TBI standard for connecting to an Ethernet PHY.
15-132
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’ connections
in the system, assuming that each PHY has a different management address.
Reduced Ten-Bit Interface (RTBI)
eTSEC
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive Data (TSEC n _RXD[4:0]/TSEC n _RXD[9:5])
Transmit Data (TSEC n _TXD[4:0]/TSEC n _TXD[9:5])
GigaBit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
Figure 15-121. eTSEC-RTBI Connection
Figure 15-121
Receive Clock (TSEC n _RX_CLK)
Management Data Clock1 (MDC)
Management Data I/O1 (MDIO)
depicts the basic components of the RTBI including the
Ethernet
Gigabit
PHY
Freescale Semiconductor
Medium
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