MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 766
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Enhanced Three-Speed Ethernet Controllers
The different interface configurations indicated by registers ECNTRL and MACCFG2 are summarized in
Table
15.5.3.1.7
PTV is a 32-bit register written by the user to store the pause duration used when the eTSEC initiates an
IEEE 802.3 PAUSE control frame via TCTRL[TFC_PAUSE]. The low-order 16 bits (PT) represent the
pause time and the high-order 16 bits (PTE) represent the extended pause control parameter. The pause
time is measured in units of pause_quanta, equal to 512 bit times. The pause time can range from 0 to
65,535 pause_quanta, or 0 to 33,553,920 bit times. See
details.
15-34
Offset eTSEC1:0x2_4028; eTSEC3:0x2_5028
Reset
15-11.
W
FIFO 8-bits
TBI 1Gbps
RTBI 1Gbps
GMII 1Gbps
RGMII 1Gbps
RGMII 100 Mbps
RGMII 10 Mbps
MII 10/100 Mbps
RMII 100 Mbps
RMII 10 Mbps
SGMII 1 Gbps
SGMII 100 Mbps
SGMII 10 Mbps
R
Figure 15-8
Interface Mode
0
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Pause Time Value Register (PTV)
describes the definition for the PTV register.
FIFM
1
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-11. eTSEC Interface Configurations
PTE
GMIIM
Figure 15-8. PTV Register Definition
0
0
0
1
1
1
1
0
0
0
0
0
0
TBIM
0
1
1
0
0
0
0
0
0
0
1
1
1
ECNTRL Field
RPM
1
0
1
0
1
1
1
0
0
0
0
0
0
All zeros
15 16
Section 15.6.3.9, “Flow Control,”
R100M
—
—
—
—
—
—
—
1
0
1
0
1
0
RMM
—
—
—
—
—
—
—
—
—
—
0
1
1
SGMIIM
0
0
0
0
0
0
0
0
0
0
1
1
1
PT
Freescale Semiconductor
MACCFG2 Field
I/F Mode
Access: Read/Write
10
10
10
10
01
01
01
01
01
10
01
01
—
for additional
31
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