MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 640
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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Local Bus Controller
14.3.1.5
The refresh timer prescaler register (MRTPR), shown in
provide the SDRAM and UPM refresh timers clock.
Table 14-11
14.3.1.6
The memory data register (MDR), shown in
array for UPM read or write commands. MDR must be set up before issuing a write command to the UPM.
Table 14-12
14-20
8–31
0–31
Offset 0x084
Reset
Bits
Bits
0–7
W
R
Offset 0x088
Reset
0
Name
Name
PTP
—
D
W
R
describes MRTPR fields.
describes MDR[D].
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Refresh timers prescaler. Determines the period of the refresh timers input clock. The system clock is divided
by PTP except when the value is 0000_0000, which represents the maximum divider of 256.
Reserved
The data to be read or written into the RAM array when a write or read command is supplied to the UPM
(M x MR[OP] = 01 or M x MR[OP] = 10).
Memory Refresh Timer Prescaler Register (MRTPR)
UPM Data Register (MDR)
PTP
Figure 14-8. Memory Refresh Timer Prescaler Register (MRTPR)
7
8
Table 14-11. MRTPR Field Descriptions
Figure 14-9. UPM Data Register (MDR)
Table 14-12. MDR Field Descriptions
Figure
14-9, contains data written to or read from the RAM
All zeros
All zeros
Description
Description
Figure
D
14-8, is used to divide the system clock to
—
Access: Read/Write
Freescale Semiconductor
Access: Read/Write
31
31
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