MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 900
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Enhanced Three-Speed Ethernet Controllers
15.6.5.2
Each eTSEC can maintain multiple TxBD rings (or transmission queues) to satisfy QoS requirements. The
ability to choose from a number of transmission streams dynamically is especially important during
periods of network congestion. Certain application such as voice and video streaming are delay sensitive,
but loss insensitive. For instance, VoIP applications require little bandwidth, but are highly sensitive to
latency. Conversely, FTP or SMTP protocols are delay insensitive, but loss sensitive.
eTSEC has a transmission scheduler that implements a programmable QoS regime. The scheduler is
responsible for choosing which of the prefetched TxBDs shall be processed next, and accordingly issuing
DMA requests to service the data stream described by the chosen BD(s). The scheduler cycle is one of:
If TCTRL[TXSCHED] is set to 00, no transmission scheduling occurs, and only TxBD ring 0 is polled for
new data to transmit, with DMACTRL controlling waiting or polling. TCTRL[TXSCHED], if not zero,
can be programmed to invoke one of two scheduling algorithms, namely priority-based queuing (PBQ),
and modified weighted round-robin queuing (MWRR). In all cases where TCTRL[TXSCHED] is not zero,
the scheduler can choose from among 1 to 8 TxBD rings per eTSEC, with individual rings being enabled
by the setting of TQUEUE[EN0–EN7] bits. For example, TxBD rings 3, 4, and 7 may be enabled for
scheduling by setting EN3, EN4, and EN7, and clearing all other EN bits.
15.6.5.2.1
PBQ is the simplest scheduler decision policy. The enabled TxBD rings are assigned a priority value based
on their index. Rings with a lower index have precedence over rings with higher indices. For example,
TxBD ring 0 has higher priority than TxBD ring 1, and TxBD ring 1 has higher priority than TxBD ring
2, and so on.
The scheduling decision is then achieved as follows:
15-168
Table
Entry
10
11
12
1. decide on a TxBD queue,
2. transmit exactly one frame from that queue, and
3. return to deciding on another queue, in step 1.
loop
9
CLE REJ AND
priority_ring = null;
ring = 0;
while priority_ring == null and ring <= 7 loop
0
0
1
0
if enabled(ring) and not ring_empty(ring) then
Transmission Scheduling
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Priority-Based Queuing (PBQ)
0
0
0
0
Table 15-145. Filer Table Example—TCP and UDP Port Filing (continued)
priority_ring = ring;
RQCTRL Fields
0
0
0
0
000_111
000_110
000_100
000_000
Q
CMP
00
00
01
01
1111
1111
0000
0000
PID
0x0000_0208 Route from UDP port 520
0x0000_0045 TFTP from UDP port 69
0x0000_0000 End cluster; default UDP: file to ring 4
0x0000_0000 By default, file to ring 0
RQPROP
Comment
Freescale Semiconductor
0x0000_000F
0x0000_180F
0x0000_1220
0x0000_0020
RQCTRL
Word
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