PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 87

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Nr.
irq(21) USB Endpoint 4
irq(22) I2C Data Transfer
irq(23) SSC Transmit
irq(24) Fast Ext. Interrupt
irq(25) Fast Ext. Interrupt
irq(26) Fast Ext. Interrupt
Note: Each entry of the interrupt vector table provides space for two word instructions or
Per interrupt node one Interrupt Control register is provided. The names of Interrupt
Control registers are composed of a part that specifies the interrupt source followed by
two letters that specify the function of register.
Table 8-2 lists the vector locations for hardware traps and the corresponding status flags
in register TFR. It also lists the priorities of trap service for cases, where more than one
trap condition might be detected within the same instruction. After any reset (hardware
reset, software reset instruction SRST, or reset by watchdog timer overflow) program
execution starts at the reset vector at location 00’0000
over every other system activity and therefore have the highest priority (trap priority III).
Software traps may be initiated to any vector location between 00’0000
A service routine entered via a software TRAP instruction is always executed on the
current CPU priority level which is indicated in bit field ILVL in register PSW. This means
that routines entered via the software TRAP instruction can be interrupted by all
hardware traps or higher level interrupt requests.
Data Sheet
one doubleword instruction. The respective vector location results from multiplying
the trap number by 4 (4 bytes per entry).
Source of Interrupt
or PEC Service
Request
Event Interrupt
Interrupt
Name
USBEP4INT
IICINTDINT
SSCTINT
FEX0INT
FEX1INT
FEX2INT
87
Enable
Flag
USBEP4IE
IICINTDIE
SSCTIE
FEX0IE
FEX1IE
FEX2IE
H
. Reset conditions have priority
Vector
Location
00’0040
00’009C
00’00B4
00’0060
00’0064
00’0068
H
H
H
H
H
H
Trap
Number
10
27
2D
18
19
1A
H
and 00’01FC
H
H
H
H
H
H
PSB 21473
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/ 24
/ 25
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Interrupts
2003-03-31
D
INCA-D
D
D
D
D
D
SFR
Adr.
FF78
FF6A
FF72
FF88
FF8A
FF8C
H
.