PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 342

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
ICD ... HDLC Interrupt from D-channel
An interrupt originated from the HDLC controller of D-channel has been recognized.
ST ... Synchronous Transfer
This interrupt is generated to enable the microcontroller to lock on to the IOM timing for
synchronous transfers. The source can be read from the STI register.
CIC ... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
TRAN ... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
Note: A read of the ISTA register clears none of the interrupts. They are only cleared by
17.6.2
Value after reset: FF
MASK
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the ISTA register can selectively be masked/disabled by setting
the corresponding bit in MASK to ’1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
reading the corresponding status register.
MASK - Mask Register
7
1
H
1
ST
IOM-2 Handler, TIC/CI Handler and HDLC Controller
CIC
342
1
TRAN
1
0
ICD
PSB 21473
2003-03-31
INCA-D
WR (60)