PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 596

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
24.4
Because the input RSTIN provides an internal pullup device, a simple connection of an
external capacitor is sufficient for an automatic power-on reset (see b) in figure above).
RSTIN may also be connected to the output of other logic gates (see a) in figure above).
Note: A power-on reset requires an active time of two reset sequences (1036 CPU clock
24.5
A dedicated register allows to issue a software reset for the HDLC Controller, the IOM-
Handler and the Transceiver. It is not necessary to apply a SW reset after a hardware
reset.
SRES - Software Reset Register (E63F
Value after reset: 00
SRES
RES_xx
0: Deactivates the reset of the functional block xx
1: Activates the reset of the functional block xx
Meaning of xx:
24.6
After the reset sequence the different groups of pins of the INCA-D are activated in
different ways depending on their function. Bus and control signals are activated
immediately after the reset sequence according to the configuration latched from
PORT0, so either external accesses can take place or the external control signals are
inactive. The general purpose I/O pins remain in input mode until reprogrammed via
software (see figure below). The RSTOUT pin remains active (low) until the end of the
initialization routine (see description).
HDLC: HDLC controller,
IOM:
TR:
The reset state is activated as long as the bit is set to ’1’
cycles) after a stable clock signal is available (about 10...50 ms to allow the on-
chip oscillator to stabilize).
IOM Handler,
Transceiver,
Power on reset
Software Reset for IOM-Handler and Transceiver
7
The INCA-D’s Pins after Reset
0
... Reset_xx
H
0
0
0
H
)
596
HDLC
RES_
RES_
XBUS-SFR
IOM
RES_
TR
0
0
System Reset
PSB 21473
2003-03-31
INCA-D