PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 598

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
24.6.2
The watchdog timer starts running after the internal reset has completed. It will be
clocked with the internal system clock divided by 2 (19.2 MHz @ f
its default reload value is 00
cycles (3.41 ms @ f
disabled, serviced or reprogrammed meanwhile. When the system reset was caused by
a watchdog timer overflow, the WDTR (Watchdog Timer Reset Indication) flag in register
WDTCON will be set to '1'. This indicates the cause of the internal reset to the software
initialization routine. WDTR is reset to '0' by an external hardware reset or by servicing
the watchdog timer. After the internal reset has completed, the operation of the watchdog
timer can be disabled by the DISWDT (Disable Watchdog Timer) instruction. This
instruction has been implemented as a protected instruction. For further security, its
execution is only enabled in the time period after a reset until either the SRVWDT
(Service Watchdog Timer) or the EINIT instruction has been executed. Thereafter the
DISWDT instruction will have no effect.
24.6.3
The DSP with its peripherals can be in either reset mode, power down mode or active
mode. During reset the DSP clears the hardware configuration registers and stops both
internal and external activity. With the first access to a read/write register the DSP enters
active mode. In this mode, normal operation takes place. The DSP with its peripherals is
reset when the RSTOUT is active. Figure 24-4 shows a state chart of the modes of the
DSP.
Figure 24-4 Operation Modes of DSP - State Chart
Watchdog Timer Operation after Reset
Reset and Power Down Mode of the DSP
CPU
R/W reg. access
=38.4 MHz) after completion of the internal reset, unless it is
H
Active
Mode
, so a watchdog timer overflow will occur 131072 CPU clock
R/W reg. access
RSTOUT=0
CCTL.PD=1
Reset
Mode
598
RSTOUT=0
Power Down
Mode
CPU
=38.4 MHz), and
System Reset
PSB 21473
2003-03-31
INCA-D