PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet
PSB21473FV13XT
Specifications of PSB21473FV13XT
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PSB21473FV13XT Summary of contents
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Data Sheet Revision History: Previous Version: Page Subjects (major changes since last revision) 52/ 173 Reset value of SYSCON modified 74 Table entries deleted 103 HDLEN bit of register PSW removed 174 Reset value of BUSCON0 corrected 181 Reset ...
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.10 Crossing Memory Boundaries 6 Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 9.7 PORT7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 15.1.6.3 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 17.3.5.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 17.5.3.8 ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . 340 17.5.3.9 MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . ...
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Table of Contents 18.9.6 ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . . 364 18.9.7 MASKTR - Mask Transceiver Interrupt . . . . . . ...
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Table of Contents 20.4.2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 22.11.6 Device Control Register (DCR 563 22.11.7 ...
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Table of Contents 24.8 System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview The INCA-D integrates all necessary functions for the completion of a digital voice terminal solution. The line transceiver of the INCA-D implements the subscriber access functions for a digital terminal to be connected to a two wire DASL ...
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Infineon Codec with DASL Transceiver and embedded Microcontroller Featuring Acoustic Echo Cancellation INCA-D Version 1.3 1.1 Features 1.1.1 16 bit CPU, Internal RAM and Memory Interface • Bootstrap Loader Function • On Chip Memory: Dual Port SRAM (2 KBytes) & ...
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Asynchronous/Synchronous Serial Interface (ASC) Full duplex asynchronous operating modes • 9-bit data frames, LSB first • Parity bit generation/checking • One or two stop bits • Baudrate from 1.5 MBaud to 0.3552 Baud (@24 MHz CPU clock) ...
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PCM A-Law/ -Law (ITU-T G.711) and 8/16-bit linear data • Two transducer correction filters • Side tone gain adjustment • Set of functional units as described (e.g. Tone Generator, DTMF Receiver) • Access to two independent 16 bit time ...
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Logical Symbols Figure 1-1 illustrates the logical symbol of the INCA-D. IOM-2 Interface DU FSC DCL I MIN1 MIN2 MIN3 HOP1 HON2 HOP2 HON2 LSP LSN BRKIN OCDS BRKOUT DPLS DMNS USB Figure 1-1 Logical Symbol TE ...
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Typical Application The following figure illustrates the typical application in which the INCA-D is usually used. Figure 1-2 Basic Configuration Data Sheet INCA-D 19 INCA-D PSB 21473 Overview Line Interface voice_te_mC.vsd 2003-03-31 ...
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Pin Descriptions 2.1 Pin Configuration The pin configuration of the INCA-D is shown in figure 2-1. IOM-2 Interface FSC DCL BCL REF BGREF MIN1 MIN2 MIN3 HOP1 HON2 HOP2 HON2 ...
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The mapping of the pin configuration to the physical device is shown in figure 2-2. 108 104 V 109 DDU DPLS DMNS V 112 SSU P6.0/CS0! P6.1/CS1! P6.2/CS2! RSTOUT! 116 RSTIN! V SS1 V DD1 P7.0/KEYSCAN0 120 P7.1/KEYSCAN1 P7.2/KEYSCAN2 P7.3/KEYSCAN3 ...
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Pin Definitions and Functions Table 2-1 Memory Interface and Control Signals Pin No. Symbol PORT0 62- P0L.0- 69 P0L.7: 52- P0H.0- 59 P0H.7: PORT1 70, 71, P1L.0- 74-79 P1L.7 80- P1H.0- 87 P1H.7 PORT4 P4.0- P4.5 95 100 PORT6 ...
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Table 2-1 Memory Interface and Control Signals (cont’d) Pin No. Symbol WR/WRL O 92 ALE Data Sheet Input (I) Function Output (O) Open Drain (OD O External Memory Read Strobe activated for every external instruction ...
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Table 2-2 Serial Interfaces,Terminal Specific Functions Pin No. Symbol Input (I) Output (O) Open Drain (OD) PORT3 I/O P3.0 - (OD possible P3.15 at all pins) 130 I/O 131 I/O 134 I/O 135 O 136 I 137 I 138 I ...
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Table 2-2 Serial Interfaces,Terminal Specific Functions (cont’d) Pin No. Symbol Input (I) Output (O) Open Drain (OD) PORT7 I/O P7.0 - (OD) P7.9 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 I/O ...
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Table 2-3 USB Interface Pin No. Symbol Input (I) Output (O) Open Drain (OD) 110 DPLS I/O 111 DMNS I/O Table 2-4 IOM-2 Interface and Strobe Signals Pin No. Symbol Input (I) Output (O) Open Drain (OD I/OD/O ...
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Table 2-5 RESET Pin No. Symbol Input (I) Output (O) Open Drain (OD) 117 RSTIN I 116 RSTOUT O 26 NMI I Table 2-6 Boundary Scan, JTAG , OCDS Pin No. Symbol Input (I) Output (O) Open Drain (OD) 105 ...
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Table 2-6 Boundary Scan, JTAG , OCDS Pin No. Symbol Input (I) Output (O) Open Drain (OD) 50 BRKIN I 51 BRKOUT O Table 2-7 Transceiver / XTAL Pin No. Symbol Input (I) Output (O) Open Drain (OD) 143 LIa ...
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Table 2-8 Analog Front End Pin No. Symbol Input (I) Output (O) Open Drain (OD REF 29 BGREF I 36 MIP1 I 35 MIN1 I 34 MIP2 I 33 MIN2 I 32 MIP3 I 31 MIN3 I ...
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Table 2-9 Pin No. Symbol Input (I) Output (O) Open Drain (OD) V 142 – DDL V 109 – DDU V 27 – DDA V 37 – DDP V 17 – DDLED V 102 – DDPLL V 119 – DD1 ...
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Architectural Overview 3.1 Functional Block Diagram Figure 3-1 Block Diagram VREF AMI A/D Dec DEC ANALOG FRONT- END ALS CORE AXO D/A Int INT AHO XRAM 4 K Bytes RESET EP Info USB (PL) PLL SIE UBL (EP0) PORT ...
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Bus Systems The Analog front End and the DSP are connected using dedicated signals which carry the AD converted and precomputed information. The remaining functional units commu- nicate over different busses. The IBUS carries synchronous data corresponding to the ...
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Clock Concept The on-chip clock generator provides the INCA-D with all necessary clock signals. Generally, the INCA-D derives its system clocks from an external crystal of 15.36 MHz connected to XTAL1 and XTAL2. An external clock signal may be ...
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Clock Generation The clock generation unit is illustrated in Figure 4-1. (3.84 - 4.17) MHz F AFE F TSF Fosc = 15.36 MHz Fout2 = (48, 38.5 MUX F 32, 24, 16) MHz DSP Fout2= 48 Mhz F AND ...
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Terminal Specific Functions The components realizing the terminal specific functions (Keypad Scanner, LED Multiplex Unit and Pulse Modulation Units) run at a frequency, which is output of divider D3. D3 can not be programmed. The clock signal for the ...
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The maximum DSP clock frequency of 48 MHz can be reduced, if the full duplex based speakerphone capability is not needed. Without any speakerphone functionality, the lowest frequency of 16 MHz is sufficient for simple phone operation. Generally, the necessary ...
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The factors have to be programmed according to Table 4-2 and Table 4-3. Table 4-2 CPU & Peripheral frequency OSC_DIV Factor D0 101 1 000 2 001 4 010 8 011 16 100 32 110 111 Table 4-3 CPU & ...
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Change the clock source back • 5 NOP instructions Note: The NOPs are necessary to ensure to have time to change the frequency while the device is running at a much higher frequency as it will be after the ...
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Register Description of the Clock Concept Unit CLK_CONF (DFAA ) CPU DSP _BYP - CPU_DIV _BYP - - Bit Function PLLEN PLL enable 0: PLL disabled Note: The PLL should ...
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Memory Organization The memory space of the INCA-D is configured in a “Von Neumann” architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, including internal Dual-Port ...
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Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) memory area. 5.1 Internal ROM (Bootstrap Loader) The INCA-D includes an internal ROM ...
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XBUS Peripherals The peripherals can be grouped into peripherals which are connected to the PD-bus (GPT, ASC, SSC) and peripherals which are connected to the XBUS (see Figure 3-1). While the PD-bus peripherals are configured by the SFR or ...
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Any word data access is made on an even byte address. The highest possible word data storage location in the internal RAM is 00’FDFE RAM can be accessed independent of the contents of the DPP registers via the PEC source ...
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Additionally, each bit in the currently active register bank can be accessed individually. Mapping of General Purpose Registers to RAM Addresses Internal RAM Address Byte Registers <CP> --- H <CP> --- H <CP> --- ...
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H DSTP7 00’FCFC SRCP7 H PEC Source and Destination Pointers 00’FCE2 DSTP0 H 00’FCE0 H SRCP0 Figure 5-3 Location of the PEC Pointers Whenever a PEC data transfer is performed, the pair of source and destination pointers, which ...
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Note: Writing to any byte of an SFR causes the non-addressed complementary byte to be cleared! The upper half of each register block is bit-addressable, so the respective control/status bits can directly be modified or checked using bit addressing. 5.9 ...
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Crossing Memory Boundaries The address space of the INCA-D is implicitly divided into equally sized blocks of different granularity and into logical memory areas. Crossing the boundaries between these blocks (code or data) or areas requires special attention to ...
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Central Processor Unit Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and to store the previously calculated ...
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The on-chip peripheral units of the INCA-D work nearly independent of the CPU. Data and control information is interchanged between the CPU and these peripherals via Special Function Registers (SFRs). Whenever peripherals need a non-deterministic CPU action, an on-chip Interrupt ...
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BACK: In this stage all external operands and the remaining operands within the internal RAM space are written back. A particularity of the INCA-D are the so-called injected instructions. These injected instructions are generated internally by the machine ...
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CPU Special Function Registers The core CPU requires a set of Special Function Registers (SFRs) to maintain the system state information, to supply the ALU with register-addressable constants and to control system and bus configuration, multiply and divide ALU ...
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The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset . SYSCON (FF12 / ...
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Note: Only exception: bit VISIBLE can also be changed by the on-chip debug support with DPEC access. System Clock Output Enable (CLKEN) The system clock output function is enabled by setting bit CLKEN in register SYSCON to '1'. If enabled, ...
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PSW (FF10 / ILVL IEN rw rw Bit Function N Negative Result Set, when the result of an ALU operation is negative. C Carry Flag Set, when the result of an ...
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The range of signed numbers extends from '–8000 word data type, or from '–80 with only one operand the N-flag represents the previous state of the specified bit. For Boolean bit operations with two operands the N-flag represents ...
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Boolean bit operations with two operands the V-flag represents the logical ORing of the two specified bits. Table 6-1 Shift Right Rounding Error Evaluation C-Flag V-Flag • Z-Flag: The Z-flag is normally ...
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CPU Interrupt Status (IEN, ILVL) The Interrupt Enable bit allows to globally enable (IEN=’1’) or disable (IEN=’0’) interrupts. The four-bit Interrupt Level field (ILVL) specifies the priority of the current CPU activity. The interrupt level is updated by hardware upon ...
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CSP (FE08 / Bit Function SEGNR Segment Number Specifies the code segment, from where the current instruction fetched. SEGNR is ignored, when segmentation ...
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Figure 6-3 Addressing via the Code Segment Pointer Note: When segmentation is disabled, the IP value is used directly as the 16-bit address. The Data Page Pointers DPP0, DPP1, DPP2, DPP3 These four non-bit addressable registers select up to ...
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DPP0 (FE00 / DPP1 (FE02 / DPP2 (FE04 / ...
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In case of the segmented memory mode the selected number of segment address bits (via bitfield SALSEL) of the respective DPP register is output on the respective segment address pins of Port 4 for all external data accesses. A DPP ...
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CP (FE10 / Bit Function cp Modifiable portion of register CP Specifies the (word) base address of the current register bank. When writing ...
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Figure 6-5 Register Bank Selection via Register CP Several addressing modes use register CP implicitly for address calculations. The addressing modes mentioned below are described in chapter “Instruction Set Summary”. Short 4-Bit GPR Addresses (mnemonic Rb) specify ...
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For single bit accesses on a GPR, the GPR's word address is calculated as just described, but the position of the bit within the word is specified by a separate additional 4-bit value. Figure 6-6 Implicit CP Use by Short ...
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Bit Function sp Modifiable portion of register SP Specifies the top of the internal system stack. The Stack Overflow Pointer STKOV This non-bit addressable register is compared against the SP register after each operation, which pushes data onto the system ...
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The Stack Underflow Pointer STKUN This non-bit addressable register is compared against the SP register after each operation, which pops data from the system stack (eg. POP and RET instructions) and after each addition to the SP register. If the ...
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The Multiply/Divide High Register MDH This register is a part of the 32-bit multiply/divide register, which is implicitly used by the CPU, when it performs a multiplication or a division. After a multiplication, this non-bit addressable register represents the high ...
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Bit Function mdl Specifies the low order 16 bits of the 32-bit multiply and divide register MD. Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to ...
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The Multiply/Divide Control Register MDC This bit addressable 16-bit register is implicitly used by the CPU, when it performs a multiplication or a division used to store the required control information for the corresponding multiply or divide operation. ...
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ZEROS (FF1C / The Constant Ones Register ONES All bits of this bit-addressable register are fixed to '1' by hardware. This ...
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Extension of Source and Destination Pointers The source and destination pointers specify the locations between which the data moved. For each of the eight PEC channels the source and destination pointers are specified by one SFR ...
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The PEC segment number registers PECSNx are defined as follows: PECSNx (Addresses see table PECDSN rw Bit Function PECSSN PEC Source Segment Number 8-bit Segment Number (address bits A23-A16) used for addressing the source of ...
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Extended PEC Channel Control The PEC control registers with the extended functionality and their application for new PEC control are defined as follows: PECCx (Addresses: see table CLT ...
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Table 6-3 PEC Control Register Addresses Register Address PECC0 FEC0 / PECC1 FEC2 / PECC2 FEC4 / PECC3 FEC6 / PECXC0 FEF0 / Long Transfer Count ...
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Channel Link Mode for Data Chaining Data chaining with linked PEC channels is enabled, if the Channel Link Control Bit in PECCx register is set to ’1’, either in one or both PEC channel control registers of a channel pair. ...
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The channel link mode is finished and the internal channel toggle flag is cleared after the last transfer of the block, if the CL flags of both pair channels are cleared. Additional Interrupt Request Node for Channel Link Interrupts The ...
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XBUS System Architecture 6.4.1 Bus Access Control CPU accesses to internal and external busses, thus internal or external memories or peripherals are controlled with the respective address ranges. These address ranges are supported for on-chip XBUS resources or for ...
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Table 6-5 Address Range and Address Range Start Definition of XADRSx register Bit Function RGSAD Address Range Start Address Selection RGSZ Address Range Size Selection F114 XBCON1(2)(3)( RDY ENx WCx - ...
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Bit Function BSWCx BUSCON Switch Control ’0’: Standard switch of bustype (switch of XBCON) ’1’: A bus wait state (Tri-state cycle) is included after execution of last old- bustype cycle and before the first new-bustype cycle after switch of XBCON ...
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READY signal). The assertion of the READY signal by the IOM2 is based on the values programmed in the IOM2 Wait States Register (IWSR). Without wait states a single c166 access takes 2 XCLK cycles. ...
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XPERCON (F024 / Reserved Bit Field Bits Type Value Description XPER1 1 rw XPER2 1 rw XPER3 1 rw XPER4 1 rw XPERx remaining bits To make an XBUS peripheral ...
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Integrated OCDS Support On Chip Debug Support (OCDS) is implemented to provide the most important hardware emulation features without special emulation chips at minimum cost. Note: For more detailed information please refer to ’OCDS C166CBC Target Specification V.1.5’ Features ...
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Features of Cerberus: • Generic serial link to address the whole user address space • External host controls all transactions • JTAG interface is used as control and data channel • Generic memory read/write functionality (RW mode) • Full support ...
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Interrupts The architecture of the INCA-D supports several mechanisms for fast and flexible response to service requests that can be generated from various sources. These mechanisms include: Normal Interrupt Processing The CPU temporarily suspends the current program execution and ...
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Interrupt System Structure The INCA-D provides separate interrupt nodes that may be assigned to 16 priority levels. Each source of an interrupt or PEC request is supplied with a separate interrupt control register and interrupt vector. ...
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Nr. Source of Interrupt or PEC Service Request irq(4) USB Endpoint 0 USB Endpoint 5-15 irq(5) IOM Data Transfer Unit irq(6) IOM Data Transfer Unit irq(7) IOM Data Transfer Unit irq(8) IOM Data Transfer Unit irq(9) IOM Data Transfer Unit ...
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Nr. Source of Interrupt or PEC Service Request irq(21) USB Endpoint 4 irq(22) I2C Data Transfer Event Interrupt irq(23) SSC Transmit irq(24) Fast Ext. Interrupt irq(25) Fast Ext. Interrupt irq(26) Fast Ext. Interrupt Note: Each entry of the interrupt vector ...
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Table 8-2 Hardware Traps and Vector Locations Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Debug Trap Class B Hardware Traps: Undefined Opcode Protected Instruction Fault ...
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Combined Interrupt Sources Some events in the INCA-D are indicated by means of a single interrupt output. Thus the interrupt request nodes irq(3), irq(4), irq(13) and irq(14) represent combined interrupt requests. Since only one interrupt line is provided, the ...
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Figure 8-1 Combined interrupts for USBINT Additionally, the Configuration, Interface and Alternate Setting Interrupt request Register (CIARI) sends an interrupt to the uC whenever the host programs multiple device configurations or interfaces. Data Sheet Device Interrupts SE0I DIRR.7 SE0IE ...
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Interrupt Node 4 (USBEPINT) The interrupt node 4 handles all interrupts that are related to the USB endpoints EP0 and EP5-EP15. The different interrupt sources are handled by the EPIEn (Endpoint Interrupt Enable Register for Endpoint n), EPIRn ((Endpoint ...
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Interrupt Node 13 (COMB1INT) The interrupts of the Keypad scanner, the PIDD (parallel interface to the DSP), IOM-2 Handler, HDLC controller and the Line transceiver are combined to interrupt node COMB1INT, which belongs to interrupt node 13. The status ...
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IRQ13_STA IRQ13_MSK STIR STIE CICIR CICIE ITRFRIR ITRFRIE PIDDIE PIDDIR TRANIR TRANIE KEYIE KEYIR HDLCIR HDLCIE COMB1INT Figure 8-3 Combined Interrupts of node 13 Data Sheet MSTI STI STOV21 STOV21 STOV20 STOV20 STOV11 STOV11 STOV10 STOV10 STI21 STI21 STI20 STI20 ...
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IRQ13_STA (DF20 • HDLCIR KEYIR rw rw Bit Value Meaning STIR INT request originating from corresponding registers CICIR (compare with Figure 8-3) ITRFRIR PIDDIR TRANIR KEYIR HDLCIR ...
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IRQ13_MSK (DF22 ) HDLCI KEYI rw rw Bit Value Meaning STI , CICI 0 Interrupt request of the dedicated source is not masked ITRFRI (compare with Figure 8-3) PIDDI TRANI KEYI ...
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Interrupt Node 14 (COMB2INT) Different interrupt sources are combined to interrupt COMB2INT as listed in Table 8-4. This interrupt belongs to interrupt node 14. The status register IRQ14_STA contains the interrupt request bits of the different interrupt sources. The ...
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IRQ14_STA (DF24 ) H • E7IR E6IR S0TIR SW2IR rw rw Bit Value Meaning (all INT request originating from corresponding source (compare with Table 8-4) 1 INT request from corresponding source IRQ14_MSK ...
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COMB2INT Figure 8-4 Combined Interrupts of node 14 8.2.5 Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sources which require PEC or interrupt processing is selected according to its interrupt priority. This priority of ...
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Interrupt Control Registers All interrupt control registers are organized identically. The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source, which is required during one round of prioritization, the upper ...
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Interrupt Enable Control Bit (individually enables/disables a specific source) ‘0’: Interrupt request is disabled ‘1’: Interrupt Request is enabled xxIR Interrupt Request Flag ‘0’: No request pending ‘1’: This source has raised an interrupt request The Interrupt Request Flag ...
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Note: Priority level 0000 is the default level of the CPU. Therefore a request on level 0 B will never be serviced, because it can never interrupt the CPU. However, an enabled interrupt request on level 0000 and reactivate the ...
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Priority Level ILVL GLVL COUNT = 00H CPU interrupt, level 1, group priority CPU interrupt, level 1, group priority ...
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PSW (FF10 / ILVL Bit Function CPU status flags (Described in section “The Central Processing Unit” page 53). MULIP Define the current ...
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Note: Traps are non-maskable and are therefore not affected by the IEN bit. 8.4 Operation of the PEC Channels The INCA-D's Peripheral Event Controller (PEC) ...
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PECCx (FECy / 6z , see table Bit Function COUNT PEC Transfer Count Counts PEC transfers and influences the channel’s action (see table below) BWT Byte / Word ...
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The table below summarizes, how the COUNT field itself, the interrupt requests flag IR and the PEC channel action depends on the previous content of COUNT. • Previous Modified IR after PEC COUNT COUNT service FF FF ‘0’ ...
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DSTP7 SRCP7 DSTP6 SRCP6 DSTP5 SRCP5 DSTP4 SRCP4 Figure 8-6 Mapping of PEC Pointers into the Internal RAM The pointer locations for inactive PEC channels may be used for general data storage. Only the required pointers occupy RAM locations. ...
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Changing the CPU level to a specific value via software blocks all requests on the same or a lower level. An interrupt source that is assigned to level 0 will be disabled and never be serviced. The ATOMIC and EXTend ...
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ILVL GLVL (Priority 8.6 Saving the Status during Interrupt Service Before an interrupt ...
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Figure 8-7 Task Status saved on the System Stack The interrupt request flag of the source that is being serviced is cleared. The IP is loaded with the vector associated with the requesting source (the CSP is cleared in ...
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Resources that are used by the interrupting program must eventually be saved and restored, eg. the DPPs and the registers of the MUL/DIV unit. 8.7 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag ...
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The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine (including N). • When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, or instruction N ...
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After an interrupt service routine has been terminated by executing the RETI instruction, and if further interrupts are pending, the next interrupt service routine will not be entered until at least two instruction cycles have been executed of the program ...
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The minimum PEC response time is 3 states (6 TCL). This requires program execution from the internal code memory, no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle. When the ...
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Note: A bus access in this context includes all delays which can occur during an external bus cycle. 8.9 External Interrupts The INCA-D provides many possibilities to react on external asynchronous events by using dedicated pins or a number of ...
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T2IE or T4IE are set, a PEC request or an interrupt request for vector T2INT or T4INT will be generated. Note: The non-maskable interrupt input pin NMI and the reset input RSTIN provide another possibility for the CPU ...
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EXICON (F1C0 / Bit Function EXIxES External Interrupt x Edge Selection Field (x=7... Fast external interrupts disabled 0 1: Interrupt on positive edge (rising Interrupt ...
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The INCA-D provides two different kinds of trapping mechanisms. Hardware traps are triggered by events that occur during program execution (eg. illegal access or undefined opcode), software traps are initiated via an instruction within the current execution flow. Software Traps ...
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Class A traps are • external Non-Maskable Interrupt (NMI) • Stack Overflow • Stack Underflow trap These traps share the same trap priority, but have an individual vector address. Class B traps are • Undefined Opcode • Protection Fault • ...
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TFR (FFAC / STK STK OCD NMI - Bit Function ILLBUS Illegal External Bus Access Flag An external access has been attempted with ...
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A class A trap occurring during the execution of a class B trap service routine will be serviced immediately. During the execution of a class A trap service routine, however, any class B trap occurring will not be serviced until ...
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Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid INCA-D opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine. The IP value pushed onto ...
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Parallel Ports The INCA-D features Port 0 (inculdes 8 bit P0H and 8 bit P0L), Port 1 (8 bit P1H and 8 bit P1L), Port 2 (14 bit), Port 3 (16 bit), Port 4 (6 bit), Port 6 (3 ...
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Data Input / Output Direction Control Registers P0L DP0LE P0H DP0HE P1L DP1LE P1H DP1HE P2 DP2 P3 DP3 P4 DP4 DP6 P6 P7 DP7 Figure 9-1 SFRs and Pins associated with the Parallel Ports Output Driver Modes In ...
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In open drain mode the upper transistor is always switched off, and the output driver can only actively drive the line to a low level. When writing a ‘1’ to the port latch, the lower transistor is switched off and ...
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OUTPUT_ENABLE_SINGLE_PIN: BSET P4.0 BSET DP4.0 OUTPUT_ENABLE_PIN_GROUP: BFLDL P4, #05H, #05H BFLDL DP4, #05H, #05H Note: When using several BSET pairs to control more pins of one port, these pairs must be separated by instructions, which do not reference the respective ...
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PORT0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halfs of PORT0 can be written (eg. via a PEC transfer) without effecting the other half. If this port is used ...
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P0L (FF00 / P0H (FF02 / Bit Function P0X.y Port data register ...
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ODP0L (FE20 / ODP0H (FE22 / Bit Function ODP0X.y Port0XOpen Drain control ...
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P0LPUDEN (FE64 / P0HPUDEN (FE66 / Bit Function P0xPUDEN.y Pulldown/Pullup Enable P0xPUDEN.y ...
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Alternate Functions of PORT0 For external memory access PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O (provided that no other bus mode ...
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Alternate Function P0H.7 P0H.6 P0H.5 P0H.4 P0H P0H.3 P0H.2 P0H.1 P0H.0 PORT0 P0L.7 P0L.6 P0L.5 P0L.4 P0L P0L.3 P0L.2 P0L.1 P0L.0 General Purpose Input/Output Demux Bus Figure 9-4 PORT0 I/O and Alternate Functions For external memory access the direction of ...
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P1L (FF04 / P1H (FF06 / Bit Function P1X.y Port data register ...
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ODP1L (FE24 / ODP1H (FE26 / Bit Function ODP1x.y Port1x Open Drain ...
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P1LPUDEN (FE70 / P1HPUDEN (FE72 / Bit Function P1xPUDEN.y Pulldown/Pullup Enable P1xPUDEN.y ...
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Alternate Functions of PORT1 When a demultiplexed external bus is enabled, PORT1 is used as address bus. Note that demultiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used for general purpose ...
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P2 (FFC0 / P2.13 P2.12 P2. Bit Function P2.y Port data register P2 bit y DP2 (FFC2 / ...
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P2PUDEN (FE7A / PUD PUD PUD - - - EN. EN. EN Bit Function P2PUDEN.y Pulldown/Pullup Enable P2PUDEN ...
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P2ALTSEL1 (F124 / Bit Function P2ALTSEL1.y Alternate Function 1Selection P2ALTSEL1 alternate function 1 selected P2ALTSEL1.y ...
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Alternate Function P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 Port 2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 General Purpose Input/Output Figure 9-6 Port 2 I/O and Alternate Functions Data Sheet a) LEDMUX10 LEDMUX9 LEDMUX8 LEDMUX7 LEDMUX6 LEDMUX5 LEDMUX4 LEDMUX3 ...
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PORT3 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP3. All port lines of P3 can be switched into push/pull or open drain mode ...
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P3PUDSEL (FE7E / P3PU P3PU P3PU P3PU P3PU DSEL. DSEL. DSEL. DSEL. DSEL Bit Function P3PUDSEL.y Pulldown/Pullup Selection P3PUDSEL ...
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P3ALTSEL0 (F126 / ALT ALT ALT ALT ALT - - - SEL0. SEL0. SEL0. SEL0. SEL0 ...
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Alternate Functions of PORT3 The pins of Port 3 serve for various functions. Table 9-2 summarizes the alternate functions of Port 3. • Alternate Functions of Port 3 Table 9-2 Port 3 Pin Alternate Function P3.0 MRST1/T5IN P3.1 MTSR1/T4EUD ...
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When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate input function, it reads the input latch, which represents the state of the pin, via the line labeled “Alternate Data Input”. When the on-chip ...
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PORT4 If this 6-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. Each port line can be switched into push/pull or open drain mode via the ...
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Bit Function ODP4.y Port 4 Open Drain control register bit y ODP4 Port line P4.y output driver in push/pull mode ODP4 Port line P4.y output driver in open drain mode P4PUDSEL (FE84 / ...
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Alternate Functions of PORT4 During external bus cycles that use segmentation (ie. an address space above 64 KByte) a number of Port 4 pins may output the segment address lines. The number of pins that is used for segment ...
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PORT6 If this 3-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the ...
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P6PUDSEL (FE90 / Bit Function P6PUDSEL.y Pulldown/Pullup Selection P6PUDSEL internal programmable pulldown transistor is selected P6PUDSEL internal programmable pullup transistor is selected ...
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Bit Function P6ALTSEL0.y Alternate Function 0 Selection P6ALTSEL alternate function 0 selected P6ALTSELy = 1: alternate function 0 selected 9.6.1 Alternate Functions of PORT6 The three chip select signals (CS2..CS0) derived from the bus control registers (BUSCON2...BUSCON0) ...
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PORT7 In the INCA-D Port 8-bit general purpose I/O port. The direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push/pull or open drain mode ...
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P7PUDSEL (FE96 / Bit Function P7PUDSEL.y Pulldown/Pullup Selection P7PUDSEL internal programmable pulldown transistor is selected P7PUDSEL internal programmable pullup transistor is selected ...
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P7ALTSEL0 (F12EA / Bit Function P7ALTSEL0.y Alternate Function 0 Selection P7ALTSEL alternate function 0 selected P7ALTSELy = 1: alternate function 0 selected Data ...
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Alternate Functions of PORT7 P7(9:0) can be used for key scan lines Table 9-5 summarizes the alternate functions of Port 7. • Alternate Functions of Port 7 Table 9-5 Port 7 Pin P7.0 P7.1 P7.2 P7.3 ...
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Dedicated Pins Most of the input/output or control signals of the functional the INCA-D are realized as alternate functions of pins of the parallel ports. There is, however, a number of signals that use separate pins, including the USB ...
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The Reference Voltage VREF can be used for biasing external components. The DC voltage at VREF is the same as at the analog in-/output pins of the analog front-end (if enabled). The Bandgap Reference Voltage BGREF (1 used ...
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The Non-Maskable Interrupt Input NMI allows to trigger a high priority trap via an external signal (eg. a power-fail signal). The NMI pin is sampled with every CPU clock cycle to detect transitions. The Oscillator Input XTAL1 and Output XTAL2 ...
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The External Bus Interface The external bus interface allows to access external peripherals and additional volatile and non-volatile memory. The external bus interface provides a number of configurations can be taylored to fit perfectly into a given ...
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External Bus Modes When the external bus interface is enabled (bit BUSACTx=’1’) and configured (bitfield BTYP), the INCA-D uses a subset of its port lines together with some control lines to build the external bus. BTYP Encoding External Data ...
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The EBC now activates the respective command signal (RD, WR, WRL, WRH). Data is driven onto the bus either by the EBC (for write cycles the ...
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After a period of time, which is determined by the access time of the memory/peripheral, data become valid. Read cycles: Input data is latched and the command signal is now deactivated. This ...
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BUSCONs are available) on the expense of the overhead for changing the registers and keeping appropriate tables. Switching between predefined address windows automatically selects the bus mode that is associated with the respective window. Predefined address ...
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Figure 11-4 Switching from Demultiplexed to Multiplexed Bus Mode The bus cycle is described in number of TCL’s, where f External Data Bus Width The EBC can operate on 8-bit or 16-bit wide external memory/peripherals. A 16-bit data bus ...
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WR serves as WRL (write low byte) and pin BHE serves as WRH (write high byte). Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE. The respective byte will be written on both ...
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Table 11-1 Coding of SALSEL SALSEL Segment Address Lines 01 None 00 Four: A19...A16 Note: The total accessible address space may be increased by accessing several banks which are distinguished by individual chip select signals. CS Signal Generation During external ...
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Upon accesses to address windows without a selected CS line all selected CS lines are deactivated. The chip select signals allow to be operated in four different modes, which are selected via bits CSWENx and CSRENx in the respective BUSCONx ...
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Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt wide range of different external bus and memory configurations with different types of memories and/or peripherals. ...
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ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers. When bit ALECTL is set to ‘1’, external bus cycles accessing the ...
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It represents the period of time during which the controller’s signals do not change. Figure 11-7 Memory Cycle Time The external bus cycles of the INCA-D can be extended for a memory or ...
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Figure 11-8 Memory Tri-State Time The output of the next address on the external bus can be delayed for a memory or peripheral, which needs more time to switch off its bus drivers, by introducing a wait state after the ...
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The data drivers from the previous bus cycle should be disabled when the RD signal becomes active. Figure 11-9 Read/Write Delay The read/write delay is controlled via the RWDCx bits in the BUSCON registers. The command(s) will be delayed, ...
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This allows to use memory components or peripherals with different interfaces within the same system, while optimizing accesses to each of them. SYSCON (FF12 / SGT STKSZ DIS rw r ...
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The layout of the five BUSCON registers is identical. Registers BUSCON4...BUSCON1, which control the selected address windows, are completely under software control, while register BUSCON0, which eg. is also used for the very first code access after reset, is partly ...
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Bit Function MCTC Memory Cycle Time Control (Number of memory cycle time wait states waitstates (Number = 15 - <MCTC> waitstates RWDCx Read/Write Delay Control ...
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ADDRSEL1 (FE18 / ADDRSEL2 (FE1A / ADDRSEL3(FE1C / ADDRSEL4 (FE1E / 0F ) ...
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Definition of Address Areas The four register pairs BUSCON4/ADDRSEL4...BUSCON1/ADDRSEL1 allow to define 4 separate address areas within the address space of the INCA-D. Within each of these address areas external accesses can be controlled by one of the four different ...
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Priority 4: If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCON0. • XBCON0 BUSCON2 BUSCON1 BUSCON0 Figure 11-10 Address Window Arbitration Note: Only the indicated overlaps are defined. All ...
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Accesses to on-chip X-Peripherals are also controlled by the EBC. However, even though an X-Peripheral appears like an external peripheral to the controller, the respective accesses do not generate valid external bus cycles. Due to timing constraints address and write ...
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The Watchdog Timer (WDT) To allow recovery from software or hardware failure, the INCA-D provides a Watchdog Timer. If the software fails to service this timer before an overflow occurs, an internal reset sequence will be initiated. This internal ...
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Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT, which is a non-bitaddressable read-only register. The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog ...
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When the watchdog timer is not disabled via instruction DISWDT, it will continue counting up, even during Idle Mode not serviced via the instruction SRVWDT by the time the count reaches FFFF reset. This reset will pull ...
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The Bootstrap Loader The built-in bootstrap loader of the INCA-D provides a mechanism to load the startup program, which is executed after reset, via the serial interface. The bootstrap loader moves code/data into the internal RAM, but it is ...
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RSTIN P0L.4 1) RxD0 TxD0 CSP:IP 1) BSL initialization time, > Zero byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host. 3) Identification byte, sent by INCA- bytes ...
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To get a rounded integer result, 18432/2 is added to numerator. So the software uses actually the following equation (T6 * FDV - 9216) / 18432 The remainder of the division will be stored. The absolute error (in ...
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In most cases 32 bytes are not sufficient for a complete loader program. Therefore this code will normally be used as a pre-loader to copy the main loader program to internal RAM with start address 00’FA60 00’FDFF . H After ...
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General Purpose Timer Unit Ports & Direction Control Alternative Functions ODP3 T2 DP3 T2EUD/CAPIN/P3.2 T2IN/P3.7 T3EUD/P3.4 T3IN/P3.6 T4EUD/P3.1 T4IN/P3.5 T5EUD/P3.9 T5IN/P3.0 T6EUD/P3.13 T6IN/P3.8 ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register ...
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Block 2 contains 2 timers/counters with a maximum resolution of f CAPREL register supports capture and reload operation with extended functionality. The following enumeration summarizes all features to be supported: l Timer Block 1: – maximum resolution. Timer ...
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Figure 14-2 Structure of Timer Block 1 14.1.1 Core Timer T3 The operation of the core timer T3 is controlled by its bitaddressable control register T3CON. Run Control The timer can be started or stopped by software through bit T3R ...
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Count Direction Control The count direction of the core timer can be controlled either by software or by the external input line T3EUD (Timer T3 External Up/Down Control Input). These options are selected by bits T3UD and T3UDE in control ...
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An overflow or underflow of timer T3 can also be used to clock other timers. For this purpose, there is the special output line T3OFL. Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by ...
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Figure 14-3 Block Diagram of Core Timer T3 in Timer Mode Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to ‘010 ’ or ‘011 ...
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Figure 14-4 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M = ‘010 ’, the timer is enabled when T3IN shows a low level. A high level at this B line stops the timer. If T3M = ...
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Figure 14-5 Block Diagram of Core Timer T3 in Counter Mode Table 14-3 Core Timer T3 (Counter Mode) Input Edge Selection T3I Triggering Edge for Counter Increment / Decrement None. Counter T3 is disabled ...
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T3 is clocked by each transition on one or both of the external input lines which gives 2- fold or 4-fold resolution of the encoder input. T3I T3IN Edge detect Phase detect T3EUD Figure 14-6 Block Diagram of Core Timer ...
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Table 14-4 Core Timer T3 (Incremental Interface Mode) Input Edge Selection T3I Triggering Edge for Counter Increment / Decrement Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD Reserved. Do ...
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Table 14-5 Core Timer T3 (Incremental Interface Mode) Count Direction Level on respective other Rising input High Down Low Up Forward T3IN T3EUD Contents of T3 Note: This example shows the timer behavior assuming that T3 counts upon any transition ...
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Forward T3IN T3EUD Contents of T3 Note: This example shows the timer behavior assuming that T3 counts upon any transition on input T3IN, i.e. T3I = ’001 Figure 14-9 Evaluation of the Incremental Encoder Signals Note: Timer T3 operating in ...
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There is no TxOUT output line for T2 and T4. l Overflow/Underflow Monitoring is not supported (no output toggle latch). Timers T2 and T4 in Counter Mode In counter mode timers T2 and T4 can be clocked either by ...
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Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. The maximum input frequency which is ...