PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 295

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

17.3
17.3.1
The HDLC controller handles layer-2 functions of the D- channel protocol (LAPD) or B-
channel protocols. It can access the D or B-channels or any combination of them e.g. 18
bit IDSL data (2B+D) via the IBUS.
It performs the framing functions used in HDLC based communication: flag generation/
recognition, bit stuffing, CRC check and address recognition.
One 64 byte FIFO for the receive and one for the transmit direction are available. They
are implemented as cyclic buffers. The transceiver reads and writes data sequentially
with constant data rate whereas the data transfer between FIFO and UBUS interface
uses a block oriented protocol with variable block sizes.
17.3.2
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a LAPD two-byte address is shown below.
•
For the address recognition the HDLC controller contains four programmable registers
for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values for the
“group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which is set to ’1’ for LAPD protocol. There are 5 different operating modes
which can be selected via the mode selection bits MDS2-0 in the MODEH register.
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
All frames with valid addresses are accepted and the bytes following the address are
transferred to the UBUS interface via RFIFO.
Transparent Mode 0 (MDS2-0 = ’110’).
Characteristics:
Data Sheet
SAPI1, 2, SAPG
High Address Byte
HDLC Controller
Overview
Message Transfer Modes
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
no address recognition
C/R 0
IOM-2 Handler, TIC/CI Handler and HDLC Controller
295
TEI 1, 2, TEIG
Low Address Byte
EA
PSB 21473
2003-03-31
INCA-D