PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 165

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

case pin WR serves as WRL (write low byte) and pin BHE serves as WRH (write high
byte). Bit WRCFG in register SYSCON selects the operating mode for pins WR and
BHE. The respective byte will be written on both data bus halfs.
When reading bytes from an external 16-bit device, whole words may be read and the
INCA-D automatically selects the byte to be input and discards the other. However, care
must be taken when reading devices that change state when being read, like FIFOs,
interrupt status registers, etc. In this case individual bytes should be selected using BHE
and A0.
Bus Mode
8-bit Multiplexed
8-bit Demultipl.
16-bit Multiplexed
16-bit Demultipl.
Note: PORT1 gets available for general purpose I/O, when none of the BUSCON
Disable/Enable Control for Pin BHE (BYTDIS)
Bit BYTDIS is provided for controlling the active low Byte High Enable (BHE) pin. The
function of the BHE pin is enabled, if the BYTDIS bit contains a '0'. Otherwise, it is
disabled and the pin can be used as standard I/O pin. The BHE pin is implicitly used by
the External Bus Controller to select one of two byte-organized memory chips, which are
connected to the INCA-D via a word-wide external data bus. After reset the BHE function
is automatically enabled (BYTDIS = '0'), if a 16-bit data bus is selected during reset,
otherwise it is disabled (BYTDIS=’1’). It may be disabled, if byte access to 16-bit memory
is not required, and the BHE signal is not used.
Segment Address Generation
During external accesses the EBC generates a (programmable) number of address lines
on Port 4, which extend the 16-bit address output on PORT0 or PORT1, and so increase
the accessible address space. The number of segment address lines is selected during
reset and coded in bit field SALSEL in register RP0H (see table below and Table 24-3,
“Code definitions of startup configurations,” on page 603).
Table 11-1
SALSEL
11
10
Data Sheet
registers selects a demultiplexed bus mode.
Segment Address Lines
Two:
Six:
Coding of SALSEL
Transfer Rate (Speed factor
for byte/word/dword access)
Very low
Low
High
Very high
A17...A16
A21...A16
( 1.5 / 3 / 6 )
( 1 / 2 / 4 )
( 1.5 / 1.5 / 3 )
( 1 / 1 / 2 )
165
Directly accessible Address Space
256
4
System Requirements
Low (8-bit latch, byte bus)
Very low (no latch, byte bus) P0H
High (16-bit latch, word bus) P1H, P1L
Low (no latch, word bus)
KByte
MByte (Maximum)
The External Bus Interface
Free I/O
Lines
P1H, P1L
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PSB 21473
2003-03-31
INCA-D