PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 283

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
IOM-2 Handler, TIC/CI Handler and HDLC Controller
17.1.5
Data transfer from and to the IOM-2 bus
In addition to the CDA registers, a mechanism of data transfer between the IOM-2 bus
and specific memory locations has been implemented. This mechanism allows
simultaneous access to all 12 time slots of an IOM-2 frame whereas up to 8 bytes (ie.
contents of 8 time slots) can be moved..For up- and downstream transfers, mask register
define which octets of the IOM-2 frame should be transferred, e.g. B1, B2, IC2 and IC4,
or to which octets data should be written respectively.
Thus the transfer direction (read/write from/to the IOM bus) and the IOM port (DU or DD)
have to be determined.
The data of selected timeslots is then moved using PEC (Peripheral Event Controller)
transfers or by regular interrupt mechanisms offered by the CPU.
The IOM-2 transfer unit consists of 8 mask register to exploit the available 8 PEC
channels. The transfers itself can be globally en- or disabled by setting the bits in the
transfer control register ITR_CR accordingly.
17.1.5.1 Data Access on IOM-2
The IOM transfer control allows the transfer of data between memory and IOM timeslots
using PEC channels. Therefore, an interrupt generation logic is provided to generate up
to eight interrupts. These interrupts may be connected to a PEC channel to trigger the
data transfer.
A mask register ITR_MSKx is provided for each interrupt. It contains a bit map of the
twelve IOM-timeslots plus control bits to indicate the IOM data line DU or DD (
ITR_MSKx.PRT) and the access direction (ITR_MSKx.DIR, RD from IOM, WR to IOM).
The software has to ensure that only one interrupt is generated per direction line and
accessed timeslot.
Note: There is no logic coordinating simultaneous access from different interrupts at the
same timeslots. The result is unpredictable.
If all current mask bits are ´0‘, a reload by a FSC pulse is enabled. As long as at least
one bit is set, reload by FSC is blocked.
The transfer interrupt generation is independent from the IOM access. The data of one
complete IOM frame is stored in a buffer containing 12 bytes. To allow a response time
of close to 125µs, two buffers are available per line and direction. One buffer is used to
fill in the data of the current IOM-2 frame, while the other one holds the data that can be
accessed by the microcontroller as described in figure Figure 17-11.
Data Sheet
283
2003-03-31