PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 43

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Any word data access is made on an even byte address. The highest possible word data
storage location in the internal RAM is 00’FDFE
RAM can be accessed independent of the contents of the DPP registers via the PEC
source and destination pointers.
The upper 256 Byte of the internal RAM (00’FD00
the current bank are provided for single bit storage, and thus they are bit addressable.
5.5
The system stack may be defined within the internal DP-RAM. The size of the system
stack is controlled by bitfield STKSZ in register SYSCON (see table below).
<STKSZ>
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
For all system stack operations the on-chip DP-RAM is accessed via the Stack Pointer
(SP) register. The stack grows downward from higher towards lower RAM address
locations. Only word accesses are supported to the system stack. A stack overflow
(STKOV) and a stack underflow (STKUN) register are provided to control the lower and
upper limits of the selected stack area. These two stack boundary registers can be used
not only for protection against data destruction, but also allow to implement a circular
stack with hardware supported system stack flushing and filling (except for option ’111’).
5.6
The General Purpose Registers (GPRs) use a block of 16 consecutive words within the
internal DP-RAM. The Context Pointer (CP) register determines the base address of the
currently active register bank. This register bank may consist of up to 16 word GPRs (R0,
R1, ..., R15) and/or of up to 16 byte GPRs (RL0, RH0, ..., RL7, RH7). The sixteen byte
GPRs are mapped onto the first eight word GPRs (see table below).
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 Byte. The GPRs are accessed via short
2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as base address
(independent of the current DPP register contents).
Data Sheet
B
B
B
B
B
B
B
B
System Stack
General Purpose Registers
Stack Size (Words)
256
128
64
32
512
---
---
1024
Internal RAM Addresses (Words)
00’FBFE
00’FBFE
00’FBFE
00’FBFE
00’FBFE
Reserved. Do not use this combination.
Reserved. Do not use this combination.
00’FDFE
43
H
H
H
H
H
H
...00’FA00
...00’FB00
...00’FB80
...00’FBC0
...00’F800
...00’F600
H
H
. For PEC data transfers, the internal
through 00’FDFF
H
H
H
H
H
H
(Note: No circular stack)
(Default after Reset)
Memory Organization
H
) and the GPRs of
PSB 21473
2003-03-31
INCA-D