PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 280

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. The TSDPx0 must be set to 08
or 88
(TS11) and the odd numbered D-channel (TS3) simultaneously on DU and DD.
17.1.4
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt
(STOV).
The CPU access to the CDAxy registers can be synchronized by means of four
programmable synchronous transfer interrupts (STIxy) and synchronous transfer
overflow interrupts (STOVxy) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
An STOVxy
acknowledged. However, if STIxy
STIxy1 which is enabled and not acknowledged.
Table 17-1 gives some examples for that. It is asumed that an STOV interrupt is only
generated because an STI interrupt was not acknowledged before.
In example 1 only the STIxy
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy
disabled. STIxy
generated due to STIxy
enabled, so STOVxy
In example 5 additionally the STIxy
generated due to STIxy
Compared to the previous example STOVxy
not generated and STOVxy
Compared to example 5 in example 7 a third STOVxy
generated additionally for both STIxy
h
for monitoring from DD respectively. By this it is possible to monitor the TIC bus
Synchronous Transfer
0
is related to its STIxy
1
is disabled but its STOVxy
0
0
and STOVxy
is enabled and generated and the corresponding STOVxy
0
0
and STOVxy
. In example 4 additionally the corresponding STOVxy
1
0
is only generated for STIxy
is enabled and thus STIxy
IOM-2 Handler, TIC/CI Handler and HDLC Controller
0
0
1
is masked, the STOVxy0 is generated for any other
and is only generated if STIxy
are both generated due to STIxy
1
0
1
is enabled with the result that STOVxy
and STIxy
is only generated due to STIxy
0
280
and xy
0
1
is disabled in example 6, so STOVxy
is enabled, and therefore STOVxy
1
.
1
are used to refer to two different
2
is enabled and thus STOVxy2 is
1
0
but not for STIxy
is only generated. If no STI is
h
for monitoring from DU
0
is enabled and not
0
.
1
.
0
PSB 21473
.
2003-03-31
INCA-D
0
is only
0
0
1
0
is
is
is
is