PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 261

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
The High-Speed Synchronous Serial Interfaces
transmitted bits is also received. Transmit data is written into the Transmit Buffer
SSCxTB. It is moved to the shift register as soon as this is empty. An SSC-master
(SSCxMS=’1’) immediately begins transmitting, while an SSC-slave (SSCxMS=’0’) will
wait for an active shift clock. When the transfer starts, the busy flag SSCxBSY is set and
a transmit interrupt request (SSCxTIR) will be generated to indicate that SSCxTB may
be reloaded again. When the programmed number of bits (2...16) has been transferred,
the contents of the shift register are moved to the Receive Buffer SSCxRB and a receive
interrupt request (SSCxRIR) will be generated. If no further transfer is to take place
(SSCxTB is empty), SSCxBSY will be cleared at the same time. Software should not
modify SSCxBSY, as this flag is hardware controlled.
The transfer of serial data bits can be programmed in many respects:
• the data width can be chosen from 2 bits to 16 bits
• transfer may start with the LSB or the MSB
• the shift clock may be idle low or idle high
• data bits may be shifted with the leading or trailing edge of the clock signal
• the baudrate may be set from 274.7 Baud up to 9 MBd (@ 36 MHz CPU clock)
• the shift clock can be generated (master) or received (slave)
This allows the adaptation of the SSCs to a wide range of applications, where serial data
transfer is required.
The Data Width Selection supports the transfer of frames of any length, from 2-bit
“characters” up to 16-bit “characters”. Starting with the LSB (SSCxHB=’0’) allows
communication eg. with ASC devices in synchronous mode (C166 family) or 8051 like
serial interfaces. Starting with the MSB (SSCHB=’1’) allows operation compatible with
the SPI interface.
Regardless which data width is selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right aligned in registers SSCxTB and SSCxRB, with the
LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for
transfer by the internal shift register logic. The unselected bits of SSCxTB are ignored,
the unselected bits of SSCxRB will be not valid and should be ignored by the receiver
service routine.
The Clock Control allows the adaptation of transmit and receive behaviour of the SSCx
to a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out
transmit data, while the other clock edge is used to latch in receive data. Bit SSCxPH
selects the leading edge or the trailing edge for each function. Bit SSCxPO selects the
level of the clock line in the idle state. So for an idle-high clock the leading edge is a
falling one, a 1-to-0 transition. The figure below is a summary.
Data Sheet
261
2003-03-31