PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 307

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
IOM-2 Handler, TIC/CI Handler and HDLC Controller
the trade-off of a doubled interrupt load. A selected block size of 32 or 16 bytes
respectively always indicates the available space in the XFIFO. So any number of bytes
smaller than the selected XFBS may be stored in the FIFO during one “write block“
access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF,XME or XRES command. XRES resets the XFIFO.
The XFIFO can hold any number of frames fitting in the 64 (M) bytes.
17.3.5.2 Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly
enough to an XPR interrupt, an XDU (transmit data underrun) interrupt will be generated.
If the HDLC channel becomes unavailable during transmission the transmitter tries to
repeat the current frame as specified in the LAPD protocol. This is impossible after the
first data block has been sent (16 or 32 bytes), in this case an XMR transmit message
repeat interrupt is set and the microcontroller has to send the whole frame again.
Both XMR and XDU interrupts cause a reset of the XFIFO. The XFIFO is locked while
an XMR or XDU interrupt is pending, i.e. all write actions of the microcontroller will be
ignored as long as the microcontroller has not read the ISTAH register with the set XDU,
XMR interrupts.
If the microcontroller writes more data than allowed (16 or 32 bytes) , then the data in the
XFIFO will be corrupted and the STAR.XDOV bit is set. If this happens, the
microcontroller has to abort the transmission by CMDR.XRES and start new.
17.3.5.3 Data Transmission Procedure
The general procedures for a data transmission sequence are outlined in the flow
diagram in figure 17-21.
Data Sheet
307
2003-03-31