PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 167

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

The chip select signals allow to be operated in four different modes, which are selected
via bits CSWENx and CSRENx in the respective BUSCONx register.
Address Chip Select signals remain active until an access to another address window.
An address chip select becomes active with the falling edge of ALE and becomes
inactive with the falling edge of ALE of an external bus cycle that accesses a different
address area. No spikes will be generated on the chip select lines.
Read or Write Chip Select signals remain active only as long as the associated control
signal (RD or WR) is active. This also includes the programmable read/write delay. Read
chip select is only activated for read cycles, write chip select is only activated for write
cycles, read/write chip select is activated for both read and write cycles (write cycles are
assumed, if any of the signals WRH or WRL gets active). These modes save external
glue logic, when accessing external devices like latches or drivers that only provide a
single enable input.
Note: CS0 provides an address chip select directly after reset when the first instruction
Segment Address versus Chip Select
The external bus interface of the INCA-D supports many configurations for the external
memory. By increasing the number of segment address lines the INCA-D can address a
linear address space of 256 KByte, 1 MByte or 4 MByte. This allows to implement a large
sequential memory area, and also allows to access a great number of external devices,
using an external decoder. By increasing the number of CS lines the INCA-D can access
memory banks or peripherals without external glue logic. These two features may be
combined to optimize the overall system performance. Enabling 4 segment address lines
and 2 chip select lines eg. allows to access two memory banks of 1 MByte each. So the
available address space is 2 MByte (without glue logic).
Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during
Data Sheet
CSWENx CSRENx Chip Select Mode
0
0
1
1
Upon accesses to address windows without a selected CS line all selected CS
lines are deactivated.
is fetched.
interrupt entry (segmentation active) or not (segmentation disabled).
0
1
0
1
Address Chip Select (Default after Reset, mode for CS0)
Read Chip Select
Write Chip Select
Read/Write Chip Select
167
The External Bus Interface
PSB 21473
2003-03-31
INCA-D