PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 76

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
The channel link mode is finished and the internal channel toggle flag is cleared after the
last transfer of the block, if the CL flags of both pair channels are cleared.
Additional Interrupt Request Node for Channel Link Interrupts
The PEC Unit has one dedicated service request node (trap number) for all channel link
interrupts. This service request node requests CPU interrupt service in case of one or
more channel link request flag and the respective enable control bit is set in the channel
link interrupt subnode control register (CLISNC). These flags indicate a channel link
interrupt condition of linked PEC channels (A and B channels) which requires support by
the CPU. The following channel link interrupt conditions requesting CPU service are
possible:
– In single transfer mode a COUNT value change from 01
– In package transfer mode a COUNT2 value change from 0001
In these cases the CPU service is requested to update the PEC control and pointer
registers while the next block transfer is executed (the whole transfer is divided into
separately controlled block transfers). The last block transfer is determined by the
missing link bit in the new (linked) PEC control register. If a new service request hits a
linked channel with count equal to zero and channel link flag disabled, a standard
interrupt is performed as known from standard PEC channels.
The channel link interrupt subnode register CLISNC is defined as follows:
CLISNC (FFA8
Bit
xxIE
xxIR
15
-
channel and CL flag is set in the respective PEC control register.
PEC channel and CL flag is set in the belonging PEC control register.
-
14
-
-
C6
13
IR
rw
H
Function
PEC Channel Link Interrupt Enable Control Bit (individually enables/disables
a specific channel pair interrupt request)
‘0’: PEC interrupt request is disabled
‘1’: PEC interrupt request is enabled
PEC Channel Service Request Flag
‘0’: No channel link service request pending
‘1’: This source (channel pair) has raised an request to service a PEC channel
after channel linking
/ D4
C6
IE
rw
12
H
)
11
-
-
10
-
-
C4
IR
9
rw
C4
IE
rw
8
SFR-b
76
7
-
-
6
-
-
C2
IR
rw
5
C2
IE
rw
4
H
Central Processor Unit
to 00
H
Reset Value: 0000
3
-
-
to 0000
H
in a linked PEC
-
2
-
PSB 21473
H
C0
2003-03-31
in a linked
IR
rw
1
INCA-D
C0
IE
rw
0
H