PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 573

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

22.12.2
Reset value: 00
The endpoint interrupt enable registers contain the endpoint specific interrupt enable
bits. With these bits, the endpoint specific interrupts can be individually enabled or
disabled. In addition to a bit in an EPIEn register the following bits have to be set to get
an interrupt active:
In case of endpoint 0 or endpoints 5-15, the global interrupt bit EPIn in GEPIR for and
the interrupt enable flag of the corresponding interrupt node USBEPIE have to be set.
Because endpoints 1-4 are handled by separate interrupt nodes, the corresponding
enable flags have to be set. (see Table 8-1)
An EPIE register is available for each of the 16 endpoints (n=0-15).
Data Sheet
EPIEn.4 Not implemented. Reserved for future use.
DNRIEn Data Not Ready Interrupt Enable
NODIEn No Data Interrupt Enable
EODIEn End of Data Interrupt Enable
RLEIEn
NAIEn
AIEn
Bit
AIEn
rw
7
Endpoint Interrupt Enable Register (EPIEn)
Acknowledge Interrupt Enable
Bit AIEn enables the generation of an endpoint specific acknowledge
interrupt when bit ACKn in register EPIRn is set.
Not Acknowledged Interrupt Enable
Bit NAIEn enables the generation of an endpoint specific not acknowledged
interrupt when bit NACKn in register EPIRn is set.
Read Length Error Interrupt Enable
Bit RLEIEn enables the generation of an endpoint specific read length error
interrupt when bit RLEn in register EPIRn is set.
Bit DNRIEn enables the generation of an endpoint specific data not ready
interrupt when bit DNRn in register EPIRn is set.
Bit NODIEn enables the generation of an endpoint specific no data interrupt
when bit NODn in register EPIRn is set.
Bit EODIEn enables the generation of an endpoint specific end of data
interrupt when bit EODn in register EPIRn is set.
H
NAIEn
rw
6
RLEIEn
rw
5
4
0
r
573
Function
DNRIEn NODIEn EODIEn SODIEn
rw
3
rw
2
rw
1
USB Module
PSB 21473
2003-03-31
INCA-D
rw
0