PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 292

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
17.2.2
C/I Channel 0
One C/I channel (called C/I0) conveys the commands and indications between the layer-
1 and the layer-2 parts of the device. C/I0 channel access may be arbitrated via the TIC
bus access protocol. In this case the arbitration is done in IOM channel 2.
The C/I0 channel is accessed via register CIR0 (in receive direction) and register CIX0
(in transmit direction). The C/I0 code is four bits long.
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
being generated anytime a change occurs and bit CIR0.CIC0 being set. A new code
must be found in two consecutive IOM frames to be considered valid and to trigger a C/
I code change interrupt status (double last look criterion).
In the transmit direction, the code written to CIX0 is continuously transmitted in C/I0.
C/I Channel 1
A second C/I channel (called C/I1) can be used to convey real time status information
between the device and various non-layer-1 peripheral devices. The C/I1 channel
consists of four or six bits in each direction. The width can be changed from 4bit to 6bit
by setting bit CIX1.CICW.
In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e.
the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received C/
I1 code is indicated by an interrupt status without double last look criterion.
17.2.3
A CIC interrupt may originate
• from a change in received C/I channel 0 code (CIC0)
or
• from a change in received C/I channel 1 code (CIC 1).
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one. Bits CIC0 and CIC1 are cleared by a read
of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
C/I channel
CIC Interrupt Logic
IOM-2 Handler, TIC/CI Handler and HDLC Controller
292
PSB 21473
2003-03-31
INCA-D