PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 575

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

In dual buffer mode, bits SODn and EODn can be set simultaneously if the
corresponding buffer page is swapped.
If a request flag in EPIRn is set, it is automatically cleared after a read operation of the
EPIRn register.
Data Sheet
EODn
SODn
End of Data
During a USB read access EODn is set if the CPU has written a
programmable number (MaxLen) of bytes in the transmit buffer. As a result,
the buffer is full and no more write actions from the CPU are allowed.
During a USB write access EODn is set if the CPU has read a
programmable number (USBLen) of bytes out of the receive buffer. As a
result, the buffer is empty now and no more read actions from the CPU are
allowed.
Start of Data
During a USB read access SODn is set if the USB has read a fixed number
(USBLen) of bytes from the transmit buffer. As a result, the buffer is now
empty and the CPU can process write actions again.
During a USB write access SODn is set if the USB has written a fixed
number (USBLen) of bytes to the receive buffer. As a result, the buffer is full
and the CPU can start read actions.
The SOD0 bit is set at the end of a status-in transfer and cleared with the
next SETUP token.
Note: The SODn interrupt is not set during a status phase.
575
USB Module
PSB 21473
2003-03-31
INCA-D