PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 42

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
Data Sheet
5.4
The peripherals can be grouped into peripherals which are connected to the PD-bus
(GPT, ASC, SSC) and peripherals which are connected to the XBUS (see Figure 3-1).
While the PD-bus peripherals are configured by the SFR or ESFR resprectively, the X-
bus peripherals (e.g. USB, I2C, IOM handler) are configured by XBUS SFR’S which are
located in the XPER area as described in Figure 5-2.
Figure 5-2
Code accesses are always made on even byte addresses. The highest possible code
storage location in the internal DP-RAM is either 00’FDFE
or 00’FDFC
instruction (unconditional), because sequential boundary crossing from internal RAM to
the SFR area is not supported and causes erroneous results.
Any word and byte data in the internal DP-RAM can be accessed via indirect or long
16-bit addressing modes, if the selected DPP register points to data page 3.
(Boot Program)
SEGMENT 1
Segment 0
IRAM/SFR
External
Memory
XRAM
External
Memory
XPER
XBUS Peripherals
H
or
for double word instructions. The respective location must contain a branch
Memory Areas and Address Space
01’0000
00’FFFF
00’8000
00’0000
H
H
H
H
42
SEGMENT 1
XBUS SFR Area
ESFR Area
SFR Area
Reserved
4 KByte
2 KByte
IRAM
XRAM
H
for single word instructions
Memory Organization
00’FFFF
00’FE00
00’F600
00’F200
00’F000
00’EFFF
00’E000
00’DFFF
00’DD00
H
H
H
H
H
H
H
H
H
PSB 21473
2003-03-31
INCA-D

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