PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 100

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
xxIE
xxIR
The Interrupt Request Flag is set by hardware whenever a service request from the
respective source occurs. It is cleared automatically upon entry into the interrupt service
routine or upon a PEC service. In the case of PEC service the Interrupt Request flag
remains set, if the COUNT field in register PECCx of the selected PEC channel
decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC
block transfer.
Note: Modifying the Interrupt Request flag via software causes the same effects as if it
Interrupt Priority Level and Group Level
The four bits of bit field ILVL specify the priority level of a service request for the
arbitration of simultaneous requests. The priority increases with the numerical value of
ILVL, so 0000
When more than one interrupt request on a specific level gets active at the same time,
the values in the respective bit fields GLVL are used for second level arbitration to select
one request for being serviced. Again the group priority increases with the numerical
value of GLVL, so 00
Note: All interrupt request sources that are enabled and programmed to the same
Upon entry into the interrupt service routine, the priority level of the source that won the
arbitration and who’s priority level is higher than the current CPU level, is copied into bit
field ILVL of register PSW after pushing the old PSW contents on the stack.
The interrupt system of the INCA-D allows nesting of up to 15 interrupt service routines
of different priority levels (level 0 cannot be arbitrated).
Interrupt requests that are programmed to priority levels 15 or 14 (ie, ILVL=111X
be serviced by the PEC, unless the COUNT field of the associated PECC register
contains zero. In this case the request will instead be serviced by normal interrupt
processing. Interrupt requests that are programmed to priority levels 13 through 1 will
always be serviced by normal interrupt processing.
had been set or cleared by hardware.
priority level must always be programmed to different group priorities. Otherwise
an incorrect interrupt vector will be generated.
Interrupt Enable Control Bit (individually enables/disables a specific
source)
‘0’: Interrupt request is disabled
‘1’: Interrupt Request is enabled
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
B
is the lowest and 1111
B
is the lowest and 11
B
is the highest priority level.
100
B
is the highest group priority.
PSB 21473
Interrupts
2003-03-31
INCA-D
B
) will