PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 362

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
18.9.1
Value after reset: 00
•
TR_
CONF0
DIS_TR
0: All layer-1 functions are enabled.
1: All layer-1 functions are disabled. The HDLC controller can still operate via IOM-2.
L1SW
0: Layer 1 state machine of the INCA-D is used
1: Layer 1 state machine is disabled. The functionality can be realized in software.
LDD
0: Clock generation after detection of any signal on the line in the power down state
1: No clock generation after detection of any signal on the line in the power down state
Note: If an interrupt is generated by the internal level detect circuitry, the CPU has to set
18.9.2
Value after reset: 64
TR_
CONF1
RPLL_INTD
0: The integrator function of the receive PLL is enabled
1: The integrator function of the receive PLL is disabled
DCL and FSC pins become input (default after reset)
The commands can be written in register TR_CMD and the status read from TR_STA.
this bit to ’0’ for an activation of the line interface.
RPLL_
TR_CONF0 - Transceiver Configuration Register
7
TR_CONF1 - Receiver Configuration Register
7
INTD
DIS_
TR
... Disable Transceiver
... Enable Layer 1 State Machine in Software
... Level Detection Discard
... Receive PLL Integrator Disable
H
H
0
1
0
1
0
0
362
L1SW
0
0
1
0
0
0
0
LDD RD/WR (30
0
Line Transceiver
RD/WR (31
PSB 21473
2003-03-31
INCA-D
H
H
)
)