PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 264

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
driven onto the line, but only held through the pullup device, the selected slave can pull
this line actively to a low level when transmitting a zero bit. The master selects the slave
device from which it expects data either by separate select lines, or by sending a special
command to this slave.
After performing all necessary initializations of the SSCx, the serial interfaces can be
enabled. For a master device, the alternate clock line will now go to its programmed
polarity. The alternate data line will go to either '0' or '1', until the first transfer will start.
After a transfer the alternate data line will always remain at the logic level of the last
transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data
transfer by writing the transmit data into register SSCxTB. This value is copied into the
shift register (which is assumed to be empty at this time), and the selected first bit of the
transmit data will be placed onto the MTSRx line on the next clock from the baudrate
generator (transmission only starts, if SSCxEN=’1’). Depending on the selected clock
phase, also a clock pulse will be generated on the SCLKx line. With the opposite clock
edge the master at the same time latches and shifts in the data detected at its input line
MRSTx. This “exchanges” the transmit data with the receive data. Since the clock line is
connected to all slaves, their shift registers will be shifted synchronously with the
master's shift register, shifting out the data contained in the registers, and shifting in the
data detected at the input line. After the preprogrammed number of clock pulses (via the
data width selection) the data transmitted by the master is contained in all slaves’ shift
registers, while the master's shift register holds the data of the selected slave. In the
master and all slaves the content of the shift register is copied into the receive buffer
SSCxRB and the receive interrupt flag SSCxRIR is set.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer
data) at pin MRSTx, when the content of the transmit buffer is copied into the slave's shift
register. It will not wait for the next clock from the baudrate generator, as the master
does. The reason for this is that, depending on the selected clock phase, the first clock
edge generated by the master may be already used to clock in the first data bit. So the
slave's first data bit must already be valid at this time.
Note: On the SSCx always a transmission and a reception takes place at the same time,
The initialization of the SCLKx pin on the master requires some attention in order to
avoid undesired clock transitions, which may disturb the other receivers. The state of the
internal alternate output lines is '1' as long as the SSCx is disabled. This alternate output
signal is ANDed with the respective port line output latch. Enabling the SSCx with an idle-
low clock (SSCxPO=’0’) will drive the alternate data output and (via the AND) the port
pin SCLKx immediately low. To avoid this, use the following sequence:
regardless whether valid data has been transmitted or received. This is different
eg. from asynchronous reception on ASC.
The High-Speed Synchronous Serial Interfaces
264
PSB 21473
2003-03-31
INCA-D