PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 579

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

CLREPn
DONEn
Data Sheet
Clear Endpoint
Setting bit CLREPn will set the address offset register for a CPU access
to USB memory to 0. The bits CBFn and UBFn will be reset when
CLREPn is set. Bit CLREPn is reset by hardware. A read operation of this
bit will always deliver 0. Setting of bit CLREPn does not change the
direction of endpoint n. This means, bit DIRn is not changed.
Note: Note: When bits CLREP0 and ESP0 are set simultaneously with
Note: Setting bits CLREPn and SETRDn or SETWRn simultaneously
Buffer Done by CPU
If bit DONE is set, the current USB memory buffer assigned to CPU is
automatically tagged full (data flow from the CPU to USB) or empty (data
flow from USB to the CPU). This bit is reset by hardware after it has been
set. A read operation of this bit always delivers a 0.
Note: If the direction of the endpoint is read (USB read access) and auto-
one instruction, bit ESP0 remains set and the next status phase is
enabled. If only CLREP0 is set, bit ESP0 is reset and the status
phase is disabled.
with one instruction is not allowed. This means that the setting of
SETRDn or SETWRn is ignored.
increment is enabled (INCEn=1) and DONEn is set, the content of
register ADROFFn is copied automatically to register EPLENn of
the actual endpoint. Register EPLENn is not changed if the auto-
increment capability is disabled (INCEn=0).
579
USB Module
PSB 21473
2003-03-31
INCA-D