PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 193

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
INCA-D
PSB 21473
General Purpose Timer Unit
x = 3
Figure 14-4 Block Diagram of Core Timer T3 in Gated Timer Mode
If T3M = ‘010
’, the timer is enabled when T3IN shows a low level. A high level at this
B
line stops the timer. If T3M = ‘011
’, line T3IN must have a high level in order to enable
B
the timer. In addition, the timer can be turned on or off by software using bit T3R. The
timer will only run, if T3R = ‘1’ and the gate is active. It will stop, if either T3R = ‘0’ or the
gate is inactive.
Note: A transition of the gate signal at line T3IN does not cause an interrupt request.
Timer 3 in Counter Mode
Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON
to ‘001
’. In counter mode timer T3 is clocked by a transition at the external input pin
B
T3IN, which is an alternate function of P3.6. The event causing an increment or
decrement of the timer can be a positive, a negative, or both a positive and a negative
transition at this line. Bit field T3I in control register T3CON selects the triggering
transition (see Table 14-3 below).
Data Sheet
193
2003-03-31

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