PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 170
PSB21473FV13XT
Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21473FV13XT.pdf
(664 pages)
Specifications of PSB21473FV13XT
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
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INCA-D
PSB 21473
The External Bus Interface
to move the data to the destination. It represents the period of time during which the
controller’s signals do not change.
Figure 11-7 Memory Cycle Time
The external bus cycles of the INCA-D can be extended for a memory or peripheral,
which cannot keep pace with the controller’s maximum speed, by introducing wait states
during the access (see figure above). During these memory cycle time wait states, the
CPU is idle, if this access is required for the execution of the current instruction.
The memory cycle time wait states can be programmed in increments of one CPU clock
within a range from 0 to 15 (default after reset) via the MCTC fields of the BUSCON
registers. 15-<MCTC> waitstates will be inserted.
Programmable Memory Tri-State Time
The INCA-D allows the user to adjust the time between two subsequent external
accesses to account for the tri-state time of the external device. The tri-state time defines,
when the external device has released the bus after deactivation of the read command
(RD).
Data Sheet
170
2003-03-31
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