PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 84

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
Interrupts
8
Interrupts
The architecture of the INCA-D supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources. These
mechanisms include:
Normal Interrupt Processing
The CPU temporarily suspends the current program execution and branches to an
interrupt service routine in order to service an interrupt requesting device. The current
program status (IP, PSW, in segmentation mode also CSP) is saved on the internal
system stack. A prioritization scheme with 16 priority levels allows the user to specify the
order in which multiple interrupt requests are to be handled.
Interrupt Processing via the Peripheral Event Controller (PEC)
A faster alternative to normal software controlled interrupt processing is servicing an
interrupt requesting device with the INCA-D's integrated Peripheral Event Controller
(PEC). Triggered by an interrupt request, the PEC performs a single word or byte data
transfer between any two locations in the whole memory space through one of eight
programmable PEC Service Channels. During a PEC transfer the normal program
execution of the CPU is halted for just 1 instruction cycle. No internal program status
information needs to be saved. The same prioritization scheme is used for PEC service
as for normal interrupt processing. PEC transfers share the 2 highest priority levels.
Trap Functions
Trap functions are activated in response to special conditions that occur during the
execution of instructions. A trap can also be caused externally by the Non-Maskable
Interrupt pin NMI. Several hardware trap functions are provided for handling erroneous
conditions and exceptions that arise during the execution of an instruction. Hardware
traps always have highest priority and cause immediate system reaction. The software
trap function is invoked by the TRAP instruction, which generates a software interrupt for
a specified interrupt vector. For all types of traps the current program status is saved on
the system stack.
External Interrupt Processing
The INCA-D allows to connect external interrupt sources and provides several
mechanisms to react on external events, including standard inputs, non-maskable
interrupts and fast external interrupts.
Data Sheet
84
2003-03-31