PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 39

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

4.8
CLK_CONF (DFAA
Bit
PLLEN
USB_DIS
LOCK
OSC_DIV
DSP_DIV
CPU_DIV
DSP_BYP
CPU_BYP
Data Sheet
_BYP
CPU
15
rw
_BYP
DSP
14
rw
Register Description of the Clock Concept Unit
13
-
Function
PLL enable
0: PLL disabled
Note: The PLL should only be disabled after the bypass for the CPU has
1: PLL enabled
USB clock disable
0: USB clock enabled
1: USB clock disabled
PLL LOCK
0: PLL not locked;
1: PLL locked, clock source switched to PLL clock if CPU_BYP is ’1’.
CPU Clock Speed
Divider value for CPU/Peripheral frequency in bypass mode (refer to Table 4-2)
DSP Clock Speed
Divider value for DSP frequency when not in bypass mode (refer to Table 4-1)
CPU Clock Speed
Divider value for CPU/Peripheral frequency when not in bypass mode (refer to
Table 4-3)
Bypass for DSP Clock
1: PLL generated signal is used;
0: Oscillators generated signal is directly used
Note: Because the LOCK bit and the DSP_BYP bit are internally ANDED, the
Bypass for CPU/Peripheral Clock
1: PLL generated signal is used;
0: Oscillators generated signal is directly used
Note: Because the LOCK bit and the CPU_BYP bit are internally ANDED, the
12
CPU_DIV
H
-
)
rw
been enabled, ie. CPU_BYP set to ’0’. Otherwise the behavior is
undefined.
clock source is set to PLL only after the PLL is locked.
clock source is set to PLL only after the PLL is locked.
11
-
10
-
9
-
DSP_DIV
XBUS-SFR
8
rw
39
7
0
6
r
LOCK
5
r
rw
4
OSC_DIV
Reset Value: 0000
rw
3
Clock Concept
rw
2
PSB 21473
_DIS
USB
2003-03-31
rw
1
INCA-D
PLL
EN
rw
0
H