PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 36

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
The maximum DSP clock frequency of 48 MHz can be reduced, if the full duplex based
speakerphone capability is not needed. Without any speakerphone functionality, the
lowest frequency of 16 MHz is sufficient for simple phone operation.
Generally, the necessary DSP frequency depends on the functional units that are
concurrently in use.
•
Table 4-1
DSP_DIV
1)
4.5
The peripherals and the CPU are provided with separated clock signals of the same
frequency. While the CPU clock is stopped during the idle mode, the peripheral clock
keeps running. Both clocks are switched off, when the power down mode is entered.
When the powerdown instruction (PWRDWN) is executed, the NMI pin must be low in
order to force the CPU to go into power down mode.
A bypass mechanism allows to run the CPU without PLL generated signals. In that case
divider D0 may be used to control the clocks for CPU and peripherals.
The bypass may be controlled by bit CPU_BYP in the CLK_CONF register.
After reset, the bypass is active, i.e. the CPU and peripheral frequency will be 7.68 MHz.
Afterwards the divider D0 can be modified or PLL generated clock signals can be
selected by software. Changing to the PLL clock has to be done only if the bit
CLK_CONF.LOCK indicates a stable PLL output clock.
The programmable divider D0 and D1 are programmed by setting bitfield OSC_DIV or
CPU_DIV respectively of register CLK_CONF to generate the clock f
the peripherals.
000
xx1
010
100
110
x means that either a ’0’ or an ’1’ can be entered
1)
Microcontroller and Peripherals
DSP Frequency
Factor
2.0
2.5
3.0
4.0
6.0
36
Resulting Frequency
48 MHz
38.5 MHz
32 MHz
24 MHz
16 MHz
CPU
Clock Concept
for the CPU and
PSB 21473
2003-03-31
INCA-D