PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 75

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Channel Link Mode for Data Chaining
Data chaining with linked PEC channels is enabled, if the Channel Link Control Bit in
PECCx register is set to ’1’, either in one or both PEC channel control registers of a
channel pair. In this case, two PEC channels are linked together and handle chained
block transfers alternatively to each other. The whole data transfer is divided into several
block transfers where each block is controlled by one PEC channel of a channel pair.
When a data block is completely transferred a channel link interrupt is generated and
the PEC service request processing is automatically switched to the ’other’ PEC channel
of the channel-pair. Thus, PEC service requests addressed to a linked PEC channel are
either handled by linked PEC channel A or by linked PEC channel B. This channel toggle
allows to set up shadow and multiple buffers for PEC transfers by changing pointer and
count values of one channel while the other channel is active. The following table list the
channels that can be linked together and the channel numbers to address the linked
channels.
Table 6-4
For each pair of linked channels, an internal channel flag, the Channel Link Toggle flag
CLT identifies which of the two PEC channels will serve the next PEC request. The CLT
flag is indicated in both PECCx registers of two linked PEC channels, where the CLT bit
in channel B always is inverse to the CLT bit in channel A. The very first transfer is
always started with the channel A if the CLT bit was not programmed otherwise before.
The CLT bit is only valid in case of linked PEC channels, indicated by the CL bits of linked
channels. If linking is not enabled, the CLT bit of both channels is always zero
(compatibility!).
The internal channel link flag CLT toggles, and the other channel begins service with the
next request if the "old" channel stops the service (COUNT=0 or COUNT2=0, dependent
on the mode), and if the new channel has in its PEC control register the CL flag enabled
and its transfer count is more than zero. Note: With the last transfer of a block transfer
(COUNT=0 or COUNT2=0), the channel link control flag CL of that channel is cleared in
its PECCx register. If the channel link flag CL of the new (chained) PEC control register
is found to be zero the whole data transfer is finished and the channel link interrupt is
coincidently a termination interrupt.
Data Sheet
PEC Channel
channel 0
channel 2
channel 4
channel 6
A
PEC Channels which could be linked together
Linked PEC Channels
PEC Channel
channel 1
channel 3
channel 5
channel 7
75
B
Linked PEC Channel
Central Processor Unit
channel 0
channel 2
channel 4
channel 6
PSB 21473
2003-03-31
INCA-D