PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 32

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
Architectural Overview
3.2
Bus Systems
The Analog front End and the DSP are connected using dedicated signals which carry
the AD converted and precomputed information. The remaining functional units commu-
nicate over different busses.
The IBUS carries synchronous data corresponding to the IOM-2 interface.It consists of
the Bit Clock, a Chip Select signal, a Read/Write strobe signal, a 3 bit address line and
8 bit lines for data in and data out.
Unlike the IBUS the UBUS is used to exchange asynchronous data which can be ac-
cessed by the CPU core via the UCIF module which connects XBUS and UBUS.
The INCA-D provides an on-chip interface (the XBUS interface), which allows to connect
integrated customer/application specific peripherals to the standard controller core. The
XBUS is an internal representation of the external bus interface, ie. it is operated in the
same way. The XBUS provides a full 24-bit address bus and a 16 bit data bus between
the CPU and its X-peripherals (the address width of external bus depends on the
selected port configuration). On XBUS, one CPU controlled access can be executed
every machine cycle. CPU accesses to XBUS peripherals are synchronous processes,
which may be delayed by programmable wait states.
The differentiation between accesses to external bus or internal XBUS is performed
within the bus controller by address range detection. For access to internal XBUS
peripherals four different address ranges can be selected, each with its own bus type
definition. To each address range belongs a chip select signal which also may be shared
between more than one X-peripheral.
For accesses to external peripherals 5 address ranges may be selected.
The Peripheral (PD) -BUS allows CPU and PEC (Peripheral Event Controller) access
to core related and generic peripherals every half machine cycle. The bus cycles are fully
synchronized without wait states. The bus also supports read-modify-write cycles with-
out performance losses. Bit modification is provided and bit protection for simultaneous
writes is also supported. However, only 512 16-bit registers can be addressed via the
demultiplexed address bus.
The RAM bus interface provides two 16 bit busses between the dual port RAM and the
CPU. Its bus cycles are fully synchronized, with a cycle time of half machine cycle. Thus,
four accesses can be made every machine cycle. This performance allows multiple GPR
(General Purpose register) accesses to occur without processor stalls. The RAM bus is
an internal bus and therefore not visible on core boundary.
Data Sheet
32
2003-03-31