PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 412

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
For a read access the command “DSP Register Read” has to be written into register
PIDDCOM. Thus the bit RDY is cleared by hardware and is set as soon as valid data are
available in register PIDDGPTC. As soon as the bit RDY is 1, the controller can read the
valid data from register PIDDGPTC.
Any change of register PIDDSTAT causes an interrupt request PIDDIR, with one
exception: This interrupt request is not generated, if the RDY bit changes, because the
DSP has been woken up from power-down by a read or write access.
Note: Generally, the interrupt request PIDDIR can only be generated after reset or after
To clear the interrupt request PIDDIR, two actions are necessary. First, the command
"Interrupt Acknowledge" must be written to the command register. Second, the status
register must be read. The interrupt is then cleared with this second action. Both actions
can be taken at any time regardless of the value of the RDY bit
The configuration register PIDDHWCFG can be read at any time. Please be aware that
the configurations must be done before the modules that are affected by the
configurations, are enabled. An easy way to ensure this is to write the configuration
register when the DSP is in power down mode.
Table 20-30 Registers seen from the uC
PIDDCLC
PIDDCOM
PIDDSTAT
PIDDHWCFG
PIDDGPTC
PIDDGPTD
1)
2)
20.2.2.1 Interrupt
The DSP can generate an interrupt to inform the CPU of an update of the PIDDSTAT
register according to table 20-31. An interrupt mask register (INTM) can be used to
disable or enable the interrupting capability of each bit of the PIDDSTAT register
individually.
Reg. name
see Chapter 23.5
This register is described in detail in Chapter 20.4.1.
an "Interrupt Acknowledge" command excuted by programming register
PIDDCOM. This is to preserve overwriting register PIDDSTAT by a new interrupt,
before the interrupt service routine of the first interrupt has read PIDDSTAT.
1)
2)
2)
2)
Clock control register of PIDD
Command register of PIDD
Status register of PIDD
Hardware configuration register
Data (general purpose) from DSP
to controller via PIDD
Data (general purpose) from
controller to DSP via PIDD
Description
412
r/w
rw
rw
rw
w
r
r
Digital Signal Processor
00’DFAC
00’DFAE
00’DFB0
00’DFB2
00’DFB4
00’DFB6
Address
H
H
H
H
H
H
PSB 21473
2003-03-31
0000
0000
0000
0000
0000
0000
Reset
INCA-D
H
H
H
H
H
H