PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 591

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

INCA-D
PSB 21473
System Reset
24
System Reset
The internal system reset function provides initialization of the INCA-D into a defined de-
fault state and is invoked either by asserting a hardware reset signal on pin RSTIN (Hard-
ware Reset Input), upon the execution of the SRST instruction (Software Reset) or by an
overflow of the watchdog timer.
The reset will deactivate the DASL-transceiver and it will abort any TIC-bus access cur-
rently in progress. The TIC-bus returns to idle.
If enabled an watchdog timeout can generate a reset on pin RSTOUT. A hardware reset
always generates a reset on pin RSTOUT.
Whenever one of the listed conditions occurs, the INCA-D is reset into its predefined de-
fault state through an internal reset procedure. When a reset is initiated, pending internal
hold states are cancelled and the current internal access cycle (if any) is completed. An
external bus cycle is aborted, except for a watchdog reset (see description). After that
the bus pin drivers and the I/O pin drivers are switched off (tristate).
The internal reset procedure requires 1024 CPU clock cycles in order to perform a com-
plete reset sequence. This reset sequence is started upon a watchdog timer overflow, a
SRST instruction or when the reset input signal RSTIN is latched low (hardware reset).
The internal reset condition is active at least for the duration of the reset sequence and
then until the RSTIN input is inactive. When this internal reset condition is removed (re-
set sequence complete and RSTIN inactive), the reset configuration is latched from
PORT0, and pins ALE, RD and WR are driven to their inactive levels.
After the internal reset condition is removed, the CPU will start program execution from
memory location 00’0000
in code segment zero. This start location will typically hold a
H
branch instruction to the start of a software initialization routine for the application spe-
cific configuration of peripherals and CPU Special Function Registers.
Data Sheet
591
2003-03-31