PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 64

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
For single bit accesses on a GPR, the GPR's word address is calculated as just
described, but the position of the bit within the word is specified by a separate additional
4-bit value.
Figure 6-6
The Stack Pointer SP
This non-bit addressable register is used to point to the top of the internal system stack
(TOS). The SP register is pre-decremented whenever data is to be pushed onto the
stack, and it is post-incremented whenever data is to be popped from the stack. Thus,
the system stack grows from higher toward lower memory locations.
Since the least significant bit of register SP is tied to '0' and bits 15 through 12 are tied
to '1' by hardware, the SP register can only contain values from F000
allows to access a physical stack within the internal RAM of the INCA-D. A virtual stack
(usually bigger) can be realized via software. This mechanism is supported by registers
STKOV and STKUN (see respective descriptions below).
The SP register can be updated via any instruction, which is capable of modifying an
SFR.
Note: Due to the internal instruction pipeline, a POP or RETURN instruction must not
SP (FE12
15
r
1
immediately follow an instruction updating the SP register.
14
r
1
H
/ 09
13
r
1
H
Implicit CP Use by Short GPR Addressing Modes
)
12
r
1
11
10
9
8
SFR
64
7
6
rw
sp
5
4
Central Processor Unit
3
Reset Value: FC00
H
2
to FFFE
PSB 21473
1
2003-03-31
INCA-D
H
0
r
. This
0
H