SAB-C167CR-LM Infineon Technologies AG, SAB-C167CR-LM Datasheet



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16-bit microcontroller with 2x2 KByte RAM
Infineon Technologies AG

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SAB-C167CR-LM Summary of contents

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... Edition 2001-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...

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C167CR Revision History: Previous Version: Page Subjects (major changes since last revision) Several Minor typos corrected 4 Pin designations corrected (pins 108, 99, 98) 5 Port 8 designations corrected Direction for P1H.4 … P1H.7 corrected 10 46 Note 4 added, ...

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Single-Chip Microcontroller C166 Family C167CR/C167SR • High Performance 16-bit CPU with 4-Stage Pipeline – 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock – 400/303 ns Multiplication (16 × 16 bit), 800/606 ns Division ( bit) ...

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... Table 1 C167CR Derivative Synopsis 1) Derivative SAK-C167SR-LM SAB-C167SR-LM SAK-C167SR-L33M SAB-C167SR-L33M SAK-C167CR-LM SAF-C167CR-LM SAB-C167CR-LM SAK-C167CR-L33M SAB-C167CR-L33M SAK-C167CR-4RM SAB-C167CR-4RM SAK-C167CR-4R33M SAB-C167CR-4R33M SAK-C167CR-16RM SAK-C167CR-16R33M 1) This Data Sheet is valid for devices manufactured in 0.5 µm technology, i.e. devices starting with and including design step GA(-T)6 ...

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Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the ...

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Pin Configuration (top view) P6.0/CS0 1 P6.1/CS1 2 P6.2/CS2 3 P6.3/CS3 4 P6.4/CS4 5 P6.5/HOLD 6 P6.6/HLDA 7 P6.7/BREQ 8 P8.0/CC16IO 9 P8.1/CC17IO 10 P8.2/CC18IO 11 P8.3/CC19IO 12 P8.4/CC20IO 13 P8.5/CC21IO 14 P8.6/CC22IO 15 P8.7/CC23IO ...

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Table 2 Pin Definitions and Functions Symbol Pin Input Num. Outp P6.6 7 I/O P6 P8.0 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P7.4 23 I/O P7.5 24 I/O P7.6 25 I/O P7 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp P2.0 47 I/O P2.1 48 I/O P2.2 49 I/O P2.3 50 I/O P2.4 51 I/O P2.5 52 I/O P2.6 53 I/O P2.7 54 I/O P2.8 57 ...

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... CLKOUT System Clock Output (= CPU Clock) Oscillator Watchdog Enable. This input enables the oscillator watchdog when high or disables it when low e.g. for testing purposes. An internal pullup device holds this input high if nothing is driving it. For normal operation pin OWE should be high or not connected ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. PORT0 IO P0L.0-7 100- 107 P0H.0-7 108, 111- 117 PORT1 IO P1L.0-7 118- 125 P1H.0-7 128- 135 P1H.4 132 I P1H.5 133 I P1H.6 134 I P1H.7 135 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. RSTIN 140 I/O RST 141 O OUT NMI 142 – AREF V 38 – AGND Data Sheet Function Reset Input with Schmitt-Trigger characteristics. A low ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num. Outp. V 17, 46, – DD 56, 72, 82, 93, 109, 126, 136, 144 V 18, 45, – SS 55, 71, 83, 94, 110, 127, 139, 143 Note: The ...

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Functional Description The architecture of the C167CR combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. ...

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... KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. ...

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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...

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... Port 4 must be limited to 4 bits (i.e. A19 … A16) in order to enable the alternate function of the CAN interface pins. CS lines can be used to increase the total amount of addressable external memory. Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs ...

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The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...

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Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C167CR is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...

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Table 3 C167CR Interrupt Nodes Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM ...

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Table 3 C167CR Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 ...

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The C167CR also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...

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Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse ...

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Table 5 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only ...

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CPU TxIN GPT2 Timer T6 Over/Underflow CCxIO 16 Capture Inputs 16 Compare Outputs CCxIO CPU GPT2 Timer T6 Over/Underflow ...

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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...

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T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 6 Block Diagram of GPT1 With its maximum resolution of ...

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The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. T5EUD CPU T5IN ...

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... In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via register P5DIDIS (Port 5 Digital Input Disable). Data Sheet 28 ...

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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...

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... The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows ...

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... Parallel Ports The C167CR provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs ...

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... Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. The oscillator watchdog can be disabled via hardware by (externally) pulling low pin OWE (internal pullup provides high level if not connected). In this case (OWE = ‘0’) the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler ...

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... BAND, BOR, AND/OR/XOR direct bit with direct bit BXOR BCMP Compare direct bit to direct bit BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 ...

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... Software Reset IDLE Enter Idle Mode PWRDN Enter Power Down Mode (supposes NMI-pin being low) SRVWDT Service Watchdog Timer DISWDT Disable Watchdog Timer EINIT Signify End-of-Initialization on RSTOUT-pin ATOMIC Begin ATOMIC sequence EXTR Begin EXTended Register sequence EXTP(R) Begin EXTended Page (and Register) sequence ...

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... The following table lists all SFRs which are implemented in the C167CR in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “ ...

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Table 7 C167CR Registers, Ordered by Name (cont’d) Name Physical Address C1LGML EF0A X --- H C1LMLM EF0E X --- H C1UAR EFn2 X --- H C1UGML EF08 X --- H C1UMLM EF0C X --- H CAPREL FE4A H CC0 ...

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Table 7 C167CR Registers, Ordered by Name (cont’d) Name Physical Address CC1IC b FF7A H CC2 FE84 H CC20 FE68 H CC20IC b F168 CC21 FE6A H CC21IC b F16A CC22 FE6C H CC22IC ...

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Table 7 C167CR Registers, Ordered by Name (cont’d) Name Physical Address CC4IC b FF80 H CC5 FE8A H CC5IC b FF82 H CC6 FE8C H CC6IC b FF84 H CC7 FE8E H CC7IC b FF86 H CC8 FE90 H CC8IC ...

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... Port 1 High Reg. (Upper half of PORT1 Port 1 Low Reg. (Lower half of PORT1 Port 2 Register H E2 Port 3 Register H E4 Port 4 Register (8 bits Port 5 Register (read only Port 5 Digital Input Disable Register H E6 Port 6 Register (8 bits Port 7 Register (8 bits Port 8 Register (8 bits C167CR C167SR Reset Value 00 H ...

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Table 7 C167CR Registers, Ordered by Name (cont’d) Name Physical Address PECC0 FEC0 H PECC1 FEC2 H PECC2 FEC4 H PECC3 FEC6 H PECC4 FEC8 H PECC5 FECA H PECC6 FECC H PECC7 FECE H PICON b F1C4 E E2 ...

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Table 7 C167CR Registers, Ordered by Name (cont’d) Name Physical Address S0EIC b FF70 H S0RBUF FEB2 H S0RIC b FF6E H S0TBIC b F19C S0TBUF FEB0 H S0TIC b FF6C H SP FE12 H SSCBR F0B4 ...

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Table 7 C167CR Registers, Ordered by Name (cont’d) Name Physical Address T2IC b FF60 H T3 FE42 H T3CON b FF42 H T3IC b FF62 H T4 FE44 H T4CON b FF44 H T4IC b FF64 H T5 FE46 H ...

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Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD V respect to ground ( ) SS Voltage on any pin with V respect to ground ( ) SS Input ...

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... Pin drivers in fast edge mode (PDCR.BIPEC = ‘0’) pF Pin drivers in reduced edge mode (PDCR.BIPEC = ‘1’) pF Pin drivers in fast edge mode MHz CPUmax ° C SAB-C167CR … ° C SAF-C167CR … ° C SAK-C167CR … - 0.5 V). The absolute sum of input overload V3.2, 2001- ...

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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167CR and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ...

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DC Characteristics (cont’d) (Operating Conditions apply) Parameter 3) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 3) Output high voltage (all other outputs) Input leakage current (Port 5) Input leakage current 4) (all other) 5) ...

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This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The READY-pullup is always ...

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I [mA] 140 120 100 Figure 8 Supply/Idle Current as a Function of Operating Frequency AC Characteristics Definition of Internal Timing The internal operation of the C167CR is controlled by the internal CPU clock edges ...

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The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Phase Locked Loop Operation f OSC f CPU Direct Clock Drive f OSC f CPU Prescaler ...

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Table 10 C167CR Clock Generation Modes CLKCFG CPU Frequency f f (P0H.7-5) = CPU OSC × OSC × OSC × OSC × ...

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TCL (see formula and × TCL the minimum value is computed using the corresponding N For a period of deviation × TCL min N where = number of consecutive TCLs ...

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... Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock ...

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AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Table 11 External Clock Drive Characteristics Parameter Symbol t Oscillator period SR 30 OSC 2) t High time Low time Rise ...

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A/D Converter Characteristics (Operating Conditions apply) Table 12 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source ...

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During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach its final voltage level within After the end of the sample time Values for the sample time t S Sample ...

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Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at Figure 12 Input Output Waveforms V + 0.1 V ...

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AC Characteristics Table 14 CLKOUT Reference Signal Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 1) The CLKOUT cycle time is influenced by the PLL jitter. For a single CLKOUT cycle (2 ...

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Table 16 External Bus Cycle Timing (Operating Conditions apply) Parameter Output delay from CLKOUT falling edge Valid for: address, BHE, early CS, write data out, ALE Output delay from CLKOUT rising edge Valid for: latched CS, ALE low Output delay ...

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General Notes For The Following Timing Figures These standard notes apply to all subsequent timing figures. Additional individual notes are placed at the respective figure. 1) The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay ...

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CLKOUT Normal ALE tc 10 Extended ALE CSxL tc 10 A23-A0, BHE, CSxE RD, RdCS D15-D0 Figure 16 Demultiplexed Bus, Read Access Data Sheet Normal ALE Cycle Extended ALE Cycle ...

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CLKOUT Normal ALE tc 10 Extended ALE CSxL tc 10 A23-A16 BHE, CSxE WRL, WRH, WR, WrCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Figure 17 Multiplexed Bus, Write Access Data Sheet Normal ALE Cycle tc 11 ...

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CLKOUT Normal ALE tc 10 Extended ALE CSxL tc 10 A23-A16 BHE, CSxE RD, RdCS AD15-AD0 (Normal ALE AD15-AD0 (Extended ALE) Figure 18 Multiplexed Bus, Read Access Data Sheet Normal ALE Cycle ...

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... MTTC waitstate this delay is zero the next following bus cycle is READY controlled, an active READY signal must be disabled before the first valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates and the ALE mode of the next following cycle. If the current cycle uses a multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time ...

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Running Cycle CLKOUT D15-D0 D15-D0 Command (RD, WR) Synchronous READY tc 25 Asynchronous 5) READY Figure 19 READY Timings Data Sheet ...

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External Bus Arbitration Table 18 Bus Arbitration Timing (Operating Conditions apply) Parameter HOLD input setup time to CLKOUT falling edge CLKOUT to BREQ delay CLKOUT to HLDA delay 1) CSx release CSx drive 1) Other signals release 1) Other signals ...

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CLKOUT tc 28 HOLD HLDA BREQ CS Other Signals Figure 20 External Bus Arbitration, Releasing the Bus Notes 1) The C167CR will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ ...

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CLKOUT HOLD HLDA BREQ CS Other Signals Figure 21 External Bus Arbitration, (Regaining the Bus) Notes 4) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by ...

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External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C167CR can be accessed (during hold states external master like an asynchronous SRAM. Table 19 XRAM Access Timing (Operating Conditions apply) Parameter Address setup time ...

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Package Outlines P-MQFP-144-6 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 69 C167CR C167SR Dimensions in mm V3.2, 2001-07 ...

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... Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher Published by Infineon Technologies AG ...

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