PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 166

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
Table 11-1
SALSEL
01
00
Note: The total accessible address space may be increased by accessing several banks
CS Signal Generation
During external accesses the EBC can generate a (programmable) number of CS lines
on Port 6, which allow to directly select external peripherals or memory banks without
requiring an external decoder. The number of CS lines is selected during reset and
coded in bits CSSEL in register RP0H (see table below and Table 24-3, “Code
definitions of startup configurations,” on page 603).
Table 11-2
When CSSEL=01 has been selected, the chip select signal CS1 has to be enabled
manually by activating the corresponding alternate function of port pin P6.1 (see
Chapter 9.6.1). Otherwise only the chip select signal CS0 is enabled. The activation of
CS0 (and the implicit selection of the alternate function of P6.0) is done automativcally
by the External Bus Controller.
The CSx outputs are associated with the BUSCONx registers and are driven active (low)
for any access within the address area defined for the respective BUSCON register. For
any access outside this defined address area the respective CSx signal will go inactive
(high). At the beginning of each external bus cycle the corresponding valid CS signal is
determined and activated. All other CS lines are deactivated (driven high) at the same
time.
Note: The CSx signals will not be updated for an access to any internal address area (ie.
(P0H.2:1)
CSSEL
1 1
1 0
0 1
0 0
which are distinguished by individual chip select signals.
when no external bus cycle is started), even if this area is covered by the
respective ADDRSELx register. An access to an on-chip X-Peripheral deactivates
all external CS signals.
None
Four:
Reserved
None
Reserved
Segment Address Lines
Coding of SALSEL
Coding of CSSEL
CS1 and CS0 availabe
Chip Select Lines
A19...A16
166
Directly accessible Address Space
64
1
pins P6.0 and P6.1usable as GP I/Os
two CS lines at pins P6.0 and P6.1 (default)
KByte (Minimum)
MByte (default)
The External Bus Interface
PSB 21473
2003-03-31
INCA-D