PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 298

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
17.3.3
17.3.3.1 General Description
The 64-byte cyclic RFIFO buffer has variable FIFO block sizes (thresholds) of 4, 8, 16 or
32 bytes, which can be selected by setting the corresponding RFBS bits in the EXMR
register. The variable block size allows an optimized HDLC processing concerning frame
length, I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and CPU is block orientated with the CPU as
master. The control of the data transfer between the CPU and the HDLC controller is
handled via interrupts (HDLC controller
controller).
There are three different interrupt indications in the ISTAH register concerned with the
reception of data:
RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
(EXMR.RFBS) can be read from RFIFO. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
RME (Receive Message End) interrupt, indicating that the reception of one message is
completed, i.e. either
a short message is received
(message length
the last part of a long message is received
(message length
and is stored in the RFIFO.
RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not be
stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the host
fails to respond quickly enough to RPF/RME interrupts since previous data was not read
by the host.
There are two control commands that are used with the reception of data:
RMC (Receive Message Complete) command, telling the HDLC controller that a data
block has been read from the RFIFO and the corresponding FIFO space can be released
for new receive data.
RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the receive
FIFO of any data (e.g. used before start of reception). It has to be used after a change
of the message transfer mode. RRES does not clear pending interrupt indications of the
receiver, but have to be be cleared by reading these interrutps.
The significant interrupts and commands are underlined as only these are usually used
during a normal reception sequence.
The following description of the receive FIFO operation is illustrated in figure 17-17 for
a RFIFO block size (threshold) of 16 and 32 bytes .
Data Reception
the defined block size (EXMR.RFBS)) or
the defined block size (EXMR.RFBS))
IOM-2 Handler, TIC/CI Handler and HDLC Controller
298
CPU) and commands (CPU
PSB 21473
2003-03-31
INCA-D
HDLC