PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 111

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Resources that are used by the interrupting program must eventually be saved and
restored, eg. the DPPs and the registers of the MUL/DIV unit.
8.7
The interrupt response time defines the time from an interrupt request flag of an enabled
interrupt source being set until the first instruction (I1) being fetched from the interrupt
vector location. The basic interrupt response time for the INCA-D is 3 instruction cycles.
•
Figure 8-8
All instructions in the pipeline including instruction N (during which the interrupt request
flag is set) are completed before entering the service routine. The actual execution time
for these instructions (eg. waitstates) therefore influences the interrupt response time.
In the figure above the respective interrupt request flag is set in cycle 1 (fetching of
instruction N). The indicated source wins the prioritization round (during cycle 2). In cycle
3 a TRAP instruction is injected into the decode stage of the pipeline, replacing
instruction N+1 and clearing the source's interrupt request flag to '0'. Cycle 4 completes
the injected TRAP instruction (save PSW, IP and CSP, if segmented mode) and fetches
the first instruction (I1) from the respective vector location.
All instructions that entered the pipeline after setting of the interrupt request flag (N+1,
N+2) will be executed after returning from the interrupt service routine.
The minimum interrupt response time is 5 states (10 TCL). This requires program
execution from the internal code memory, no external operand read requests and setting
the interrupt request flag during the last state of an instruction cycle. When the interrupt
request flag is set during the first state of an instruction cycle, the minimum interrupt
response time under these conditions is 6 state times (12 TCL).
Data Sheet
Pipeline Stage
FETCH
DECODE
EXECUTE
WRITEBACK
IR-Flag
Interrupt Response Times
Pipeline Diagram for Interrupt Response Time
1
0
Cycle 1
N
N - 1
N - 2
N - 3
Interrupt Response Time
Cycle 2
N + 1
N
N - 1
N - 2
111
Cycle 3
N + 2
TRAP (1)
N
N - 1
Cycle 4
I1
TRAP (2)
TRAP
N
PSB 21473
Interrupts
2003-03-31
INCA-D