PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 413

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Table 20-31 Interrupt Source Summary
An interrupt is internally generated if any combination of these events occurs and the
interrupt is not masked. The interrupts are issued immedeately after the status register
update. The status register update for the event set bit DTV or ABT is performed
immediately after the event occurs that causes the bit to be set. For the event clear bit
DTV the status register update is performed with the next update of the RDY bit, i.e., up
to 125 us after the event occurs that causes the bit to be set. For the event clear bit TG,
the status register update is performed 125 us after the update of the RDY bit as the
latest.
This internal interrupt is cleared only when the host executes the Data Read Access with
Interrupt Acknowledge command. In this case, the internal interrupt is cleared when the
first bit of the PIDDSTAT register is output. If a new event occurs while the host reads
the status register, the status register is updated after the current access is terminated
and a new interrupt is internally generated immediately after the access has ended.
20.2.2.2 Abort
If the DSP detects a corrupted configuration (e.g. due to a transient loss of power) it
stops operation and initializes all read/write registers to their reset state. The DSP
discards all commands with the exception of a write command to the revision register
while ABT is set. Only after the write command to the revision register (with any value)
the ABT bit is reset and a reinitialization can take place.
20.2.2.3 Revision Register
The INCA-D contains a revision register. This register is read only and does not influence
operation in any way. A write to the revision register clears the ABT bit of the STATUS
register but does not alter the content of the revision register.
Data Sheet
STATUS
(old)
RDY=0
TG=1
DTV=0
DTV=1
ABT=0
STATUS
(new)
RDY=1
TG=0
DTV=1
DTV=0
ABT=1
Set by
Command completed
Tone generator active
DTMF tone detected
DTMF tone lost or EN=0
Exception (non-maskable)
413
Reset by
Command issued
Tone sequence finished
or EN=0
DTMF tone lost or EN=0
DTMF tone detected
Write to REV Register
Digital Signal Processor
PSB 21473
2003-03-31
INCA-D