PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 263

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
Figure 16-5 Full Duplex Configuration (valid for SSC0 and SSC1)
The data output pins MRSTx of all slave devices are connected together onto the one
receive line in this configuration. During a transfer each slave shifts out data from its shift
register. There are two ways to avoid collisions on the receive line due to different slave
data:
Only one slave drives the line, ie. enables the driver of its MRSTx pin. All the other
slaves have to program their MRSTx pins to input. So only one slave can put its data
onto the master's receive line. Only receiving of data from the master is possible. The
master selects the slave device from which it expects data either by separate select
lines, or by sending a special command to this slave. The selected slave then switches
its MRSTx line to output, until it gets a deselection signal or command.
The slaves use open drain output on MRSTx. This forms a Wired-AND connection.
The receive line needs an external pullup in this case. Corruption of the data on the
receive line sent by the selected slave is avoided, when all slaves which are not selected
for transmission to the master only send ones (‘1’). Since this high level is not actively
Data Sheet
Master
Shift Register
Clock
Device #1
MTSR
SCLK
MRST
The High-Speed Synchronous Serial Interfaces
Receive
Clock
Transmit
263
Device #2
Device #3
MTSR
MTSR
SCLK
SCLK
MRST
MRST
Clock
Clock
Shift Register
Shift Register
PSB 21473
2003-03-31
MCS01963
INCA-D
Slave
Slave

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