PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 240

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
Figure 15-5 Asynchronous 9-Bit Frames
In wake-up mode received frames are only transferred to the receive buffer register, if
the 9th bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt request will be ac-
tivated and no data will be transferred.
This feature may be used to control communication in multi-processor system:
When the master processor wants to transmit a block of data to one of several slaves, it
first sends out an address byte which identifies the target slave. An address byte differs
from a data byte in that the additional 9th bit is a '1' for an address byte and a '0' for a
data byte, so no slave will be interrupted by a data 'byte'. An address 'byte' will interrupt
all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the 8
LSBs of the received character (the address). The addressed slave will switch to 9-bit
data mode (eg. by clearing bit CON_M.0), which enables it to also receive the data bytes
that will be coming (having the wake-up bit cleared). The slaves that were not being ad-
dressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes.
IrDA Frames
The modulation schemes of IrDA is based on standard asynchronous data transmission
frames. The asynchronous data format in IrDA mode (S0CON_M=010
follows :
1 start bit / 8 data bits / 1 stop bit
The coding/decoding of/to the asynchronous data frames is shown in Figure 15-6. In
general, during the IrDA transmissions UART frames are encoded into IR frames and
vice cersa. A low level on the IR frame indicates a “LED off“ state. A high level on the IR
frame indicates a “LED on“ state.
For a “0“ bit in the UART frame a high pulse is generated. For a “1“ bit in the UART frame
no pulse is generated. The high pulse starts in the middle of a bit cell and has a fixed
Start
Bit
0
LSB
D0
D1
D2
11-/12-Bit UART Frame
D3
9 Data Bits
D4
The Asynchronous / Synchr. Serial Interface
240
D5
S0CON_M=100
S0CON_M=101
S0CON_M=111
D6
D7
Bit 9
B
B
B
: Bit 9 = Wake-up Bit
: Bit 9 = Data Bit D8
: Bit 9 = Parity Bit
(1st)
Stop
Bit
1
(2nd)
Stop
Bit
1
B
) is defined as
PSB 21473
2003-03-31
INCA-D