PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 182

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
When the watchdog timer is not disabled via instruction DISWDT, it will continue
counting up, even during Idle Mode. If it is not serviced via the instruction SRVWDT by
the time the count reaches FFFF
reset. This reset will pull the external reset indication pin RSTOUT low. It differs from a
software or external hardware reset in that bit WDTR (Watchdog Timer Reset Indication
Flag) of register WDTCON will be set. A hardware reset or the SRVWDT instruction will
clear this bit. Bit WDTR can be examined by software in order to determine the cause of
the reset.
A watchdog reset will also complete a running external bus cycle before starting the
internal reset sequence
Note: After a hardware reset that activates the Bootstrap Loader the watchdog timer will
To prevent the watchdog timer from overflowing, it must be serviced periodically by the
user software. The watchdog timer is serviced with the instruction SRVWDT, which is a
protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads
the high byte of the watchdog timer register WDT with the preset value from bitfield
WDTREL which is the high byte of register WDTCON. Servicing the watchdog timer will
also reset bit WDTR. After being serviced the watchdog timer continues counting up from
the value (<WDTREL> * 2
the chance of unintentionally servicing the watchdog timer (eg. by fetching and executing
a bit pattern from a wrong location) is minimized. When instruction SRVWDT does not
match the format for protected instructions the Protection Fault Trap will be entered,
rather than the instruction be executed.
The time period for an overflow of the watchdog timer is programmable in two ways:
• the input frequency to the watchdog timer can be selected via bit WDTIN in register
WDTCON to be either f
• the reload value WDTREL for the high byte of WDT can be programmed in register
WDTCON.
The period P
therefore be determined by the following formula:
Note: For safety reasons, the user is advised to rewrite WDTCON each time before the
be disabled.
watchdog timer is serviced
WDT
between servicing the watchdog timer and the next overflow can
P
WDT
CPU
8
/2 or f
). Instruction SRVWDT has been encoded in such a way that
=
2
(1 + <WDTIN>*6)
H
CPU
the watchdog timer will overflow and cause an internal
/128.
182
* (2
16
f
CPU
- <WDTREL> * 2
The Watchdog Timer (WDT)
8
)
PSB 21473
2003-03-31
INCA-D