PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 338

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PSB21473FV13XT

Manufacturer Part Number
PSB21473FV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21473FV13XT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Lead Free Status / RoHS Status
Compliant
Data Sheet
17.5.3.6 IOM_CR - Control Register IOM Data
Value after reset: : 01
IOM_CR
SPU
0: The DU line is normally used for transmitting data
1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1
After a subsequent CIC-interrupt (C/I-code change; ISTA) and reception of the C/I-code
”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM
command as C/I-code in the CIX0-register, resets the SPU bit and wait for the following
CIC-interrupt.
CI_CS ... C/I Channel Selection
The channel selection for D-channel and C/I-channel is done in the channel select bits
CS2-0 of register TR_CR (for the transceiver) and DCI_CR (for the D-channel controller
and C/I-channel controller).
0: A write access to CS2-0 has effect on the configuration of D- and C/I-channel,
whereas a read access deliveres the D-channel configuration only.
1: A write access to CS2-0 has effect on the configuration the C/I-channel only and a
read access deliveres the C/I-channel configuration only.
TIC_DIS
0: The last octet of the last IOM time slot (TS 11) is treated as TIC bus
1: The last octet of the last IOM time slot is treated as any other timeslot. No TIC-bus
Note: to use the build-in TIC-bus handler, it must be enabled additionally in MODEH
EN_BCL
0: The BCL clock is disabled
1: The BCL clock is enabled
CLKM
If the transceiver is disabled (DIS_TR = ’1’) the DCL from the IOM-2 interface is an input.
With
devices to deliver IOM-clocking.
handling possible.
7
SPU
... Software Power UP
... TIC Bus Disable
... Enable Bit Clock BCL
... Clock Mode
H
0
;
CI_CS TIC_
IOM-2 Handler, TIC/CI Handler and HDLC Controller
DIS
338
EN_
BCL
CLKM DIS_
OD
0
DIS_
IOM
RD/WR (57
PSB 21473
2003-03-31
INCA-D
H
)

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