PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 646

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
•
Demultiplexed Bus
ALE cycle time = 4 TCL + 2
The following timings are valid for a CPU frequency of 32 MHz.
Parameter
ALE high time
Address setup to ALE
ALE falling edge to RD, WR (with RW-
delay)
ALE falling edge to RD, WR (no RW-
delay)
RD, WR low time
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address hold after WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
1)
2)
(with RW-delay)
(no RW-delay)
(with RW-delay)
(no RW-delay)
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
2)
1)
2)
2)
t
A
+
t
C
+
t
F
(62.5 ns at 32 MHz CPU clock without waitstates)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
6
8
9
12
13
14
15
16
17
18
22
24
26
28
38
39
41
646
min.
29 +
16 +
17 +
2 +
62 +
79 +
112 +
63 +
51 +
32 +
38 +
0.5 -
50 +
t
Max. CPU Clock
A
t
t
t
t
t
t
t
t
t
t
t
A
A
A
C
C
C
F
F
F
A
F
t
Electrical Characteristics
F
32 MHz
max.
39 +
53 +
54 +
67 + 2
1.0 -
46 +
t
t
t
t
t
C
C
A
A
C
t
A
+
+ 2
PSB 21473
+
t
C
2003-03-31
t
t
C
A
INCA-D
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns