PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 107

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

•
Figure 8-6
The pointer locations for inactive PEC channels may be used for general data storage.
Only the required pointers occupy RAM locations.
Note: If word data transfer is selected for a specific PEC channel (ie. BWT=’0’), the
8.5
Interrupt and PEC service requests from all sources can be enabled, so they are
arbitrated and serviced (if they win), or they may be disabled, so their requests are
disregarded and not serviced.
Enabling and disabling interrupt requests may be done via three mechanisms:
Control Bits allow to switch each individual source “ON” or “OFF”, so it may generate a
request or not. The control bits (xxIE) are located in the respective interrupt control
registers. All interrupt requests may be enabled or disabled generally via bit IEN in
register PSW. This control bit is the “main switch” that selects, if requests from any
source are accepted or not.
For a specific request to be arbitrated the respective source’s enable bit and the global
enable bit must both be set.
The Priority Level automatically selects a certain group of interrupt requests that will be
acknowledged, disclosing all other requests. The priority level of the source that won the
arbitration is compared against the CPU’s current level and the source is only serviced,
if its level is higher than the current CPU level.
Data Sheet
respective source and destination pointers must both contain a valid word address
which points to an even byte boundary. Otherwise the Illegal Word Access trap will
be invoked, when this channel is used.
Prioritization of Interrupt and PEC Service Requests
Mapping of PEC Pointers into the Internal RAM
SRCP7
SRCP6
SRCP5
SRCP4
DSTP7
DSTP6
DSTP5
DSTP4
00’FCFE
00’FCFC
00’FCFA
00’FCF8
00’FCF6
00’FCF4
00’FCF2
00’FCF0
H
H
H
H
H
H
H
H
107
SRCP3
SRCP2
SRCP1
SRCP0
DSTP3
DSTP2
DSTP1
DSTP0
00’FCEE
00’FCEC
00’FCEA
00’FCE8
00’FCE6
00’FCE4
00’FCE2
00’FCE0
H
H
H
H
H
H
H
H
PSB 21473
Interrupts
2003-03-31
INCA-D