PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 108

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

Data Sheet
Changing the CPU level to a specific value via software blocks all requests on the same
or a lower level. An interrupt source that is assigned to level 0 will be disabled and never
be serviced.
The ATOMIC and EXTend instructions automatically disable all interrupt requests for
the duration of the following 1...4 instructions. This is useful eg. for semaphore handling
and does not require to re-enable the interrupt system after the unseparable instruction
sequence.
Interrupt Class Management
An interrupt class covers a set of interrupt sources with the same importance, ie. the
same priority from the system’s viewpoint. Interrupts of the same class must not interrupt
each other. The INCA-D supports this function with two features:
Classes with up to 4 members can be established by using the same interrupt priority
(ILVL) and assigning a dedicated group level (GLVL) to each member. This functionality
is built-in and handled automatically by the interrupt controller.
Classes with more than 4 members can be established by using a number of adjacent
interrupt priorities (ILVL) and the respective group levels (4 per ILVL). Each interrupt
service routine within this class sets the CPU level to the highest interrupt priority within
the class. All requests from the same or any lower level are blocked now, ie. no request
of this class will be accepted.
The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities,
depending on the number of members in a class. A level 6 interrupt disables all other
sources in class 2 by changing the current CPU level to 8, which is the highest priority
(ILVL) in class 2. Class 1 requests or PEC requests are still serviced in this case.
The 19 interrupt sources (excluding PEC requests) are so assigned to 3 classes of
priority rather than to 7 different levels, as the hardware support would do.
Table 8-5
(Priority)
ILVL
15
14
13
12
11
10
9
X
X
3
Software controlled Interrupt Classes (Example)
X
GLVL
2
X
1
X
0
Interpretation
PEC service on up to 8 channels
Interrupt Class 1
5 sources on 2 levels
108
PSB 21473
Interrupts
2003-03-31
INCA-D