PSB21473FV13XT Infineon Technologies, PSB21473FV13XT Datasheet - Page 237

• Manufacturer Part Number: PSB21473FV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21473FV13XT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Compliant

15.1.4
Parity, framing, and overrun error detection is provided to increase the reliability of data
transfers. Transmission and reception of data is double-buffered. For multiprocessor
communication, a mechanism to distinguish address from data bytes is included. Testing
is supported by a loop-back option. A 13-bit baudrate timer with a versatile input clock
divider circuitry provides the ASC with the serial clock signal.
A transmission is started by writing to the Transmit Buffer register S0TBUF. Only the
number of data bits which is determined by the selected operating mode will actually be
transmitted, ie. bits written to positions 9 through 15 of register S0TBUF are always in-
significant.
Data transmission is double-buffered, so a new character may be written to the transmit
buffer register, before the transmission of the previous character is complete. This allows
the transmission of characters back-to-back without gaps.
Data reception is enabled by the Receiver Enable Bit CON_REN. After reception of a
character has been completed, the received data and, if provided by the selected oper-
ating mode, the received parity bit can be read from the (read-only) Receive Buffer reg-
ister S0RBUF. Bits in the upper half of S0RBUF which are not valid in the selected
operating mode will be read as zeros.
Data reception is double-buffered, so that reception of a second character may already
begin before the previously received character has been read out of the receive buffer
register. In all modes, receive buffer overrun error detection can be selected through bit
CON_OEN. When enabled, the overrun error status flag CON_OE and the error interrupt
request line EIR will be acitvated when the receive buffer register has not been read by
the time reception of a second character is complete. The previously received character
in the receive buffer is overwritten.
The Loop-Back option (selected by bit CON_LB) allows the data currently being trans-
mitted to be received simultaneously in the receive buffer. This may be used to test serial
communication routines at an early stage without having to provide an external network.
In loop-back mode the alternate input/output function of port pins is not required.
Note: Serial data transmission or reception is only possible when the Baudrate
15.1.5
Asynchronous mode supports full-duplex communication, where both transmitter and re-
ceiver use the same data frame format and the same baudrate. Data is transmitted on
pin P3.10/TXD and received on pin P3.11/RXD.
IrDA data transmission/reception is supported up to 115.2 KBit/s. Figure 15-3 shows the
block diagram of the ASC_P3 when operating in asynchronous mode.
Data Sheet
Generator Run Bit CON_R is set to ‘1’. Otherwise the serial interface is idle.
Do not program the mode control field COM_M to one of the reserved
combinations to avoid unpredictable behaviour of the serial interface
General Operation
Asynchronous Operation
The Asynchronous / Synchr. Serial Interface
237
PSB 21473
2003-03-31
INCA-D